A web based tool for teaching hardware design based on the plain simple hardware description language

2014 ◽  
Author(s):  
Karsten Becker
Keyword(s):  
Hardware Design ◽  
Hardware Description Language ◽  
Description Language ◽  
Web Based ◽  
Hardware Description

Will proof replace simulation?

1992 ◽  
Vol 339 (1652) ◽  
pp. 21-33
Keyword(s):  
Circuit Design ◽  
Hardware Design ◽  
Daily Basis ◽  
Hardware Description Language ◽  
Test Cases ◽  
Description Language ◽  
Theorem Provers ◽  
Familiar Environment ◽  
Hardware Description ◽  
Complete Circuit

Within industry, the almost universally accepted method of validating a design against its requirement involves extrapolation from simulation of a (comparatively) small number of test cases to the behaviour of the complete circuit. That such an extrapolation is in general unjustifiable is widely accepted, but despite theorem provers’ ability to provide a mo^e robust link between specification and circuit design, very few industrial engineers are using theorem provers on a daily basis. This paper aims to consider some of the factors that may be preventing the wider application of proof methods. Specifically, RSRE has concentrated on two areas of research: the development of a largely automatic but functionally limited proof system, and more recently on a more general prover based on the concepts of a hardware description language. It is hoped to illustrate that these provers, being designed specifically for hardware design applications, may provide a more familiar environment for designers wishing to do proofs.

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

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