Will proof replace simulation?

Within industry, the almost universally accepted method of validating a design against its requirement involves extrapolation from simulation of a (comparatively) small number of test cases to the behaviour of the complete circuit. That such an extrapolation is in general unjustifiable is widely accepted, but despite theorem provers’ ability to provide a mo^e robust link between specification and circuit design, very few industrial engineers are using theorem provers on a daily basis. This paper aims to consider some of the factors that may be preventing the wider application of proof methods. Specifically, RSRE has concentrated on two areas of research: the development of a largely automatic but functionally limited proof system, and more recently on a more general prover based on the concepts of a hardware description language. It is hoped to illustrate that these provers, being designed specifically for hardware design applications, may provide a more familiar environment for designers wishing to do proofs.

Author(s):  
Shaila S Math ◽  
Manjula R B

Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs. The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components. AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation module takes 160ns and for single write operation it takes 565ns.


2013 ◽  
Vol 433-435 ◽  
pp. 1438-1447
Author(s):  
Wan Fu Huang

Most simple digital clocks use a push button to increment time reading for time adjustment. It is often time consuming. This paper suggests adding a four-by-four keypad to adjust each single time digit. The required valid 4x4 keypad key set for each time digit is predefined in the circuit design. Pressing a prohibited key would neither generate any function nor affect the operation of the digital clock. The system prototype circuit design was based on Verilog hardware description language and implemented on an EVS6 Boardan FPGA lab board. With the proposed design, adjusting time on a digital clock is quick and easy.


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