Design and implementation of 4 bit Flash ADC using low power low offset dynamic comparator

2015 ◽  
Author(s):  
Suman Biswas ◽  
Jitendra Kumar Das ◽  
Rajendra Prasad
Keyword(s):  
Low Power ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Low Offset

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

scholarly journals A low-power dynamic comparator for low-offset applications

Integration ◽  
2019 ◽  
Vol 69 ◽  
pp. 23-30 ◽  
Author(s):  
Ata Khorami ◽  
Roghayeh Saeidi ◽  
Manoj Sachdev ◽  
Mohammad Sharifkhani
Keyword(s):  
Low Power ◽  
Dynamic Comparator ◽  
Power Dynamic ◽  
Low Offset

A novel low offset low power CMOS dynamic comparator

2018 ◽  
Vol 96 (1) ◽  
pp. 147-158 ◽  
Author(s):  
Priyesh P. Gandhi ◽  
N. M. Devashrayee
Keyword(s):  
Low Power ◽  
Dynamic Comparator ◽  
Low Power Cmos ◽  
Low Offset

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC

2014 ◽  
Vol 35 (5) ◽  
pp. 055008 ◽  
Author(s):  
Shubin Liu ◽  
Zhangming Zhu ◽  
Yintang Yang ◽  
Lianxi Liu
Keyword(s):  
Low Power ◽  
High Speed ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Low Offset
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