A Low-Power 3-5-GHz UWB Down-Converter with Resistive-Feedback LNA in a 90-nm CMOS Process

2008 ◽  
Author(s):  
Giuseppina Sapone ◽  
Giuseppe Palmisano
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Resistive Feedback ◽  
5 Ghz ◽  
Resistive Feedback Lna

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

Low-power CMOS LNA based on dual resistive-feedback structure with peaking inductor for wideband application

2013 ◽  
Vol 5 (1) ◽  
pp. 65-70 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Output Stage ◽  
Chip Area ◽  
Inductive Peaking ◽  
Resistive Feedback ◽  
Low Power Cmos ◽  
Noise Amplifier

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

scholarly journals A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

2016 ◽  
Vol 2016 ◽  
pp. 1-9 ◽  
Author(s):  
Noushin Ghaderi ◽  
Hamid Reza Erfani-jazi ◽  
Mehdi Mohseni-Mirabadi
Keyword(s):  
Low Power ◽  
Dead Zone ◽  
Optimization Methods ◽  
Phase Locked Loop ◽  
Open Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Locking Range ◽  
Charge Pump Circuit ◽  
5 Ghz

A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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