Structural optimization of fine pitch, large die flip chip package

2005 ◽  
Author(s):  
A.G.K. Viswanath ◽  
Wang Fang ◽  
Tai-Chong Chai ◽  
Navas Khan ◽  
S. Sampath
Keyword(s):  
Structural Optimization ◽  
Flip Chip ◽  
Fine Pitch

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

Combined Manufacture Methods for High Density LTCC Substrates: Thick Film Screen Printing, Ink Jet, Postfiring Thin Film Processes, and Laser-Drilled Fine Vias

2009 ◽  
Vol 6 (1) ◽  
pp. 6-12 ◽  
Author(s):  
Arne Albertsen ◽  
Koji Koiwai ◽  
Kyoji Kobayashi ◽  
Tomonori Oguchi ◽  
Katsumi Aruga
Keyword(s):  
Thin Film ◽  
Thick Film ◽  
Screen Printing ◽  
Flip Chip ◽  
High Density ◽  
Uv Laser ◽  
Fine Pitch ◽  
Ink Jet ◽  
Printing Ink ◽  
Base Substrate

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

Advancements in Flip Chip Assembly Equipment and Processes

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001328-001358 ◽  
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Daniel Buergi
Keyword(s):  
Flip Chip ◽  
First Generation ◽  
Standard Process ◽  
Productivity Improvement ◽  
Gate Arrays ◽  
Fine Pitch ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Pros And Cons ◽  
Bonding Method

High I/O devices such as microprocessors, applications processors and field programmable gate arrays have transitioned from wire bonding to flip chip interconnect as the I/O densities have increased above 2000. As the bump pitch shrinks the standard process flow for production flip chip processes is challenged. As the bump pitch continues to shrink the accuracy of standard flip chip bonders is not adequate for the fine pitch packages of tomorrow. The options to resolve this issue are extending the accuracy for standard flip chip bonders or moving the assembly of these packages to the inherently more accurate thermo-compression bonders. This paper will discuss the pros and cons of each approach along with showing data which indicates what accuracies are actually required. Although substrate manufacturers have developed low CTE designs which mitigate the warpage caused by the mismatch between the Si die and the substrate as the assembled package travels through the reflow oven, warpage at finer pitches is becoming more and more difficult to control in flip chip processes. Thermocompression (TC) bonding is seen as the next-generation packaging technology that will resolve this issue through local reflow of the solder and elimination of the reflow oven. Despite the tremendous technical and quality advantages of TC bonding, adoption has been limited by the relatively low throughput of the first generation thermocompression bonders. In this paper we describe bonding results obtained with an innovative flip chip bonding method to optimize the process to dramatically improve the throughput by applying flux directly to the substrate rather than dipping the pillars in a bath. A study of this process and comparison of various methods of accomplishing it along with their related costs are discussed in the paper. A second large productivity improvement that is promising by eliminating the need for cooling the die before transferring die that has pre-applied underfill film laminated to it is also studied with productivity models developed. Finally a unique equipment concept for managing the transition from mass reflow to thermo-compression bonding will be presented.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-18
Author(s):  
Phani Vallabhajosyula
Keyword(s):  
Visual Inspection ◽  
Flip Chip ◽  
Print Quality ◽  
Solder Paste ◽  
3D Measurement ◽  
Aperture Size ◽  
Fine Pitch ◽  
Technology Applications ◽  
Component Assembly ◽  
Special Step

Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

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