Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

Flip-Chip Ball Grid Array Lead-Free Solder Joint Under Reliability Test

2005 ◽  
Vol 127 (4) ◽  
pp. 446-451 ◽  
Author(s):  
Ming-Hwa R. Jen ◽  
Lee-Cheng Liu ◽  
Jenq-Dah Wu
Keyword(s):  
Mechanical Properties ◽  
High Temperature ◽  
Service Time ◽  
Flip Chip ◽  
Failure Modes ◽  
Mechanical Responses ◽  
Operational Life ◽  
Different Temperatures ◽  
Free Solder

The work is aimed to investigate the mechanical responses of bare dies of the combination of pure tin∕Al–NiV–Cu Under bump metallization (UBM) and packages of pure tin∕Al–NiV–Cu UBM/substrate of standard thickness of aurum. The mechanical properties under multiple reflow and long term high temperature storage test (HTST) tests at different temperatures and the operational life were obtained. A scanning electron microscope was used to observe the growth of IMC and the failure modes in order to realize their reaction and connection. From the empirical results of bare dies, the delamination between IMC and die was observed due to the tests at 260 °C multiple reflow. However, their mechanical properties were not affected. Nevertheless, the bump shear strength of bare dies were decreased by HTST tests. In package, all the results of mechanical properties by multiple reflow test and HTST test were significantly lowered. It was shown that the adhesion between bump and die reduced obviously as tests going on. As for high temperature operational life test in the conditions of 150 °C and 320 mA (5040A∕cm2), the average stable service time of the package was 892 h, and the average ultimate service time of the package was 1053 h.

Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2004 ◽  
Vol 126 (3) ◽  
pp. 359-366 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Aging Process ◽  
Flip Chip ◽  
Initial Period ◽  
Bulk Solder ◽  
The Body ◽  
Nano Indentation ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine pitch flip chip assembly processes. The solder bumps and joints that were aged at either 80 °C or 150 °C for up to 440 hours (∼18 days); have been studied by an analysis using micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼50 hours) as compared to the non-aged bumps, but a decrease after longer aging (e.g. 440 hours). A brittle Ag3Sn phase formed as large stick-like features in the body of bulk solder and near the interface of solder/UBM during the initial aging, and is attributed with the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the body of solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a large lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process at 150 °C. These are believed to be detrimental to joint reliability.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

2007 ◽  
Vol 10 (4-5) ◽  
pp. 133-142 ◽  
Author(s):  
Jung-Tang Huang ◽  
Pen-Shan Chao ◽  
Hou-Jun Hsu ◽  
Sheng-Hsiung Shih
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Fine Pitch ◽  
Solder Bumps

Interactions Between Flip Chip Underfill and Solder Alloy

2010 ◽  
Vol 132 (3) ◽  
Author(s):  
D. Blass ◽  
P. Borgesen
Keyword(s):  
Solder Alloy ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Moisture Sensitivity ◽  
Complex Issue ◽  
Shock Testing ◽  
Out Of Plane ◽  
Level 3 ◽  
Mechanical Optimization

The effects of underfill selection on flip chip reliability were always a complex issue. Mechanical optimization of the underfill performance, achieved by the addition of appropriate fillers, is invariably a tradeoff between the adhesion and the coefficient of thermal expansion (CTE) and, thus, also between in-plane and out-of-plane stresses. Another critical concern is the degradation of the underfill in processing and/or long term exposure to operating temperatures and ambient humidity. This is strongly affected by the chemical compatibility with combinations of solder mask, chip passivation, and flux residues. The latter is believed to be responsible for our observation of interactions with the solder alloy, too. As for the effects of glass transition temperatures and CTE, we find materials that were close to optimum for eutectic SnPb to be very far from the best options for lead free joints. We report on two sets of systematic experiments. The first addressed the performance of combinations of underfills, no-clean fluxes, and solder alloys in a JEDEC level 3 moisture sensitivity test. The second one involved thermal shock testing of flip chip assemblies underfilled with one of five different materials after soldering with SnCu, SAC305, and SnPb.

A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects

2005 ◽  
Author(s):  
Bing Dang ◽  
Paul J. Joseph ◽  
Xiaojin Wei ◽  
Muhannad S. Bakir ◽  
Paul A. Kohl ◽  
...  
Keyword(s):  
Heat Transfer ◽  
Heat Sink ◽  
Flip Chip ◽  
Microchannel Heat Sink ◽  
Front Side ◽  
Thermal Interface ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cmos Compatible ◽  
Board Level

We demonstrate a prototype chip-scale microfluidic cooling scheme. CMOS compatible processes allow the monolithic integration of the microchannel heat sink into the backside of a Si chip at low temperature (≤260°C). At the front side of a chip, fine pitch area-array solder bumps are fabricated by electroplating for high-density electrical I/O interconnection, while a peripheral array of micro polymer pipes are fabricated as thermal-fluidic I/O interconnects. The resulting “microfluidic flip chip” can be bonded onto a liquid-cooled board substrate using conventional flip-chip assembly processes. The cooling liquid can, therefore, be transferred into a Si chip directly from the board-level manifolds to alleviate the thermal interface issues.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.

Sign in / Sign up

Export Citation Format

Share Document