QC-LDPC can bring a higher coding gain to the FSO system, but the complexity of the decoding algorithm restricted its application in high-speed FSO system.In this paper, it adopts an improved Modified Min-sum Algorithm (MMSA) to reduce the decoding complexity and save decoding time. In this paper, the author programs the decoder with VHDL Hardware Description Language and analyzes the static time of the design with Synplify Pro and QuartusII to verify the correctness. Moreover, each functional unit is downloaded to the EP3C16Q240C8 chip produced by ALTERA Company and encapsulated into the IP core. Finally, we used MATLAB software to build the FSO system for testing decoder performance. The results show that the QC-LDPC decoder based on FPGA has higher reliability in FSO system.
High-Speed Decoders for Polar Codes