Low Power High Gain Fully Integrated CMOS Power Amplifier using Power Combining and Mode Locking Architecture

2020 ◽  
Author(s):  
C Vijaya Bhaskar ◽  
P Munaswamy
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
High Gain ◽  
Mode Locking ◽  
Power Combining ◽  
Fully Integrated

Broadband low-power amplifier with high gain and mixer modes using quantum-well GaAs FET technology

1992 ◽  
Vol 28 (13) ◽  
pp. 1241 ◽  
Author(s):  
P. Wennekers ◽  
R. Bosch ◽  
W. Reinert ◽  
A. Huelsmann ◽  
G. Kaufel ◽  
...  
Keyword(s):  
Quantum Well ◽  
Low Power ◽  
Power Amplifier ◽  
High Gain

High-Q Coupled-Coil Power-Combining Technique for Fully Integrated CMOS Power Amplifier

2020 ◽  
Author(s):  
Matthew Love ◽  
Mury Thian ◽  
Floris van der Wilt ◽  
Koen van Hartingsveldt ◽  
Kave Kianush
Keyword(s):  
Power Amplifier ◽  
Power Combining ◽  
Fully Integrated ◽  
High Q

scholarly journals High-Gain and Low-Power Power Amplifier for 24-GHz Automotive Radars

2015 ◽  
Vol 9 (2) ◽  
pp. 27-34 ◽  
Author(s):  
Shin-Gon Kim ◽  
Habib Rastegar ◽  
Min Yoon ◽  
Chul-Woo Park ◽  
Kyoungyong Park ◽  
...  
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
High Gain ◽  
Automotive Radars ◽  
24 Ghz

scholarly journals Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
The Novel ◽  
Ultra Low Power ◽  
Design And Optimization ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Insertion Losses

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

scholarly journals A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 257 ◽  
Author(s):  
Se-Eun Choi ◽  
Hyunjin Ahn ◽  
Joonhoi Hur ◽  
Kwan-Woo Kim ◽  
Ilku Nam ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Cmos Process ◽  
Power Combining ◽  
Fully Integrated ◽  
Term Evolution ◽  
Class D ◽  
Adjacent Channel ◽  
On Chip

This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 µm CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than −30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz.

Fully-integrated 32 dBm, 1.5–2.9 GHz SiGe-bipolar power amplifier using power-combining transformer

2005 ◽  
Vol 41 (16) ◽  
pp. 908 ◽  
Author(s):  
A. Vasylyev ◽  
P. Weger ◽  
W. Bakalski ◽  
W. Simbürger
Keyword(s):  
Power Amplifier ◽  
Power Combining ◽  
Fully Integrated
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