Gilbert cell Mixer design in 65nm CMOS technology

This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 μm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply.

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Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$\mu{\hbox {m}}$ CMOS Technology

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.2008.919053 ◽

2008 ◽

Vol 56 (4) ◽

pp. 835-848 ◽

Cited By ~ 43

Author(s):

Hwann-Kaeo Chiou ◽

Tsung-Yu Yang

Keyword(s):

Cmos Technology ◽

Low Loss ◽

Mixer Design

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A Four-Channel CMOS Front-End for Interference-Robust GNSS Receiver

Electronics ◽

10.3390/electronics9020291 ◽

2020 ◽

Vol 9 (2) ◽

pp. 291

Author(s):

Fang Han ◽

Jian Gao ◽

Xiaoran Li ◽

Zhiming Chen

Keyword(s):

Local Oscillator ◽

Cmos Technology ◽

Satellite System ◽

Low Noise ◽

Low Noise Amplifiers ◽

Third Order ◽

Front End ◽

Mixer Design ◽

Linearity Improvement ◽

Global Navigation Satellite

A four-channel receiver front-end is designed and implemented for interference- and jamming-robust global navigation satellite system (GNSS) in a 0.18-μm CMOS technology. The front-end consists of four identical RF-to-IF signal paths including low-noise amplifiers (LNAs), mixers and IF amplifiers. In addition, it also includes a phase-locked loop (PLL), which synthesizes the local oscillator (LO) signal, and a serial peripheral interface (SPI) for parameter adjustment. To improve the interference and jamming robustness, a novel linearity improvement technology and LO duty cycle adjustment method are applied in LNA and mixer design, respectively. The receiver achieves a gain of 40 dB, an input-referred third-order intercept point (IIP3) of −8 dBm and a jammer-to-signal power ratio (JSR) of 72 dB under 1.8-V and 3.3-V supply, while occupying a 4 × 5 mm2 die area including the electrostatic discharge (ESD) I/O pads.

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