An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V

In recent years, there has been a growing interest in the application of ferroelectric thin films for nonvolatile memory applications and as a gate insulator in DRAM structures. In addition, bulk ferroelectric materials are also widely used as components in electronic circuits and find numerous applications in sensors and actuators. To a large extent, the performance of ferroelectric materials are governed by the ferroelectric domains (with dimensions in the micron to sub-micron range) and the switching of domains in the presence of an applied field. Conventional TEM studies of ferroelectric domains structures, in conjunction with in-situ studies of the domain interactions can aid in explaining the behavior of ferroelectric materials, while providing some answers to the mechanisms and processes that influence the performance of ferroelectric materials. A few examples from bulk and thin film ferroelectric materials studied using the TEM are discussed below.Figure 1 shows micrographs of ferroelectric domains obtained from undoped and Fe-doped BaTiO3 single crystals. The domain boundaries have been identified as 90° domains with the boundaries parallel to <011>.

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Epitaxial ferroelectric thin films

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100170591 ◽

1994 ◽

Vol 52 ◽

pp. 572-573

Author(s):

S. G. Ghonge ◽

E. Goo ◽

R. Ramesh ◽

R. Haakenaasen ◽

D. K. Fork

Keyword(s):

Single Crystal ◽

Work Function ◽

Nonvolatile Memory ◽

Ferroelectric Properties ◽

Electrical Contact ◽

Memory Devices ◽

Ferroelectric Films ◽

Si Substrates ◽

Electro Optic ◽

Wide Range

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.

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High Quality HfO2 Film and Its Applications in Novel Poly-Si Devices

MRS Proceedings ◽

10.1557/proc-716-b2.6 ◽

2002 ◽

Vol 716 ◽

Author(s):

K.L. Ng ◽

N. Zhan ◽

M.C. Poon ◽

C.W. Kok ◽

M. Chan ◽

...

Keyword(s):

Barrier Height ◽

Nonvolatile Memory ◽

Dielectric Material ◽

Tunneling Current ◽

Interface Layer ◽

Si Substrate ◽

Hfo2 Film ◽

Effective Barrier Height ◽

Effective Barrier ◽

Nonvolatile Memory Devices

AbstractHfO2 as a dielectric material in MOS capacitor by direct sputtering of Hf in an O2 ambient onto a Si substrate was studied. The results showed that the interface layer formed between HfO2 and the Si substrate was affected by the RTA time in the 500°C annealing temperature. Since the interface layer is mainly composed of hafnium silicate, and has high interface trap density, the effective barrier height is therefore lowered with increased RTA time. The change in the effective barrier height will affect the FN tunneling current and the operation of the MOS devices when it is applied for nonvolatile memory devices.

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Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory

IEICE Transactions on Electronics ◽

10.1587/transele.e96.c.714 ◽

2013 ◽

Vol E96.C (5) ◽

pp. 714-717

Author(s):

Woo Young CHOI ◽

Min Su HAN ◽

Boram HAN ◽

Dongsun SEO ◽

Il Hwan CHO

Keyword(s):

Nonvolatile Memory ◽

Sacrificial Layer

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Root Cause Analysis for Pin Leakage

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0217 ◽

2016 ◽

Author(s):

Zhigang Song ◽

Jochonia Nxumalo ◽

Manuel Villalobos ◽

Sweta Pendyala

Keyword(s):

Failure Analysis ◽

Root Cause Analysis ◽

Advanced Technology ◽

Process Step ◽

Cause Analysis ◽

Hard Mask ◽

Technology Node ◽

Root Cause ◽

Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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