scholarly journals Analysing the effect of process variation to reduce parametric yield loss

2008 ◽  
Author(s):  
H. Ramakrishnan ◽  
S. Shedabale ◽  
G. Russell ◽  
A. Yakovlev
Keyword(s):  
Yield Loss ◽  
Process Variation ◽  
Parametric Yield

OPTIMIZATION OF PARAMETRIC YIELD: A TUTORIAL

1992 ◽  
Vol 03 (01) ◽  
pp. 95-136 ◽  
Author(s):  
STEPHEN W. DIRECTOR ◽  
PETER FELDMANN ◽  
KANNAN KRISHNA
Keyword(s):  
Manufacturing Process ◽  
Yield Loss ◽  
The Other ◽  
Parametric Yield ◽  
Other Hand ◽  
Different Types

Yield loss can be characterized as either catastrophic or parametric. Catastrophic yield loss is primarily due to local disturbances, such as spot defects, that occur in a manufacturing process. On the other hand, parametric yield loss is due to global disturbances, such as mask misalignment. In this paper we briefly explore these two different types of yield loss and then review some methods that have been developed to maximize parametric yield.

Multidimensional physical design optimization for systematic and parametric yield loss reduction

2007 ◽  
Author(s):  
L. N. Karklin ◽  
A. Arkhipov ◽  
Y. Belenky ◽  
C. Decoin ◽  
D. Lay ◽  
...  
Keyword(s):  
Design Optimization ◽  
Yield Loss ◽  
Physical Design ◽  
Loss Reduction ◽  
Parametric Yield

Yield Enhancement due to Addition of Bevel Cleans at Middle of Line(MOL) Zone

2018 ◽  
Vol 282 ◽  
pp. 329-333
Author(s):  
Tsultrim Tharchin ◽  
Elango Balu ◽  
Sherjang Singh
Keyword(s):  
Yield Loss ◽  
Process Variation ◽  
Yield Enhancement ◽  
Technology Nodes ◽  
Wafer Edge

As the technology nodes become smaller and smaller the circuit dies get closer and closer to the edge of the wafer. Defects and issues on the bevel are seen to cause issues such as flaking and blocked plating on the dies at the edge of the wafer. This drastically increases the need for a clean wafer edge as the issues directly translate to yield loss at the end of the line. The wafer edge and backside are shown to have a significant impact on yield as well as process variation [1]. Introducing a dilute HF and SC1 bevel clean at the MOL layer resolves flaking and defect issues found on the bevel. Dispensing it on the backside of the wafer and ensuring that the chemistry is rolled over to the bevel results in the backside of the wafer becoming cleaner and helps resolve overlay issues. All the above stated effects are seen to result in an overall edge gain in edge yield.

Elemental chlorine-free bleaching of North American hardwood kraft pulps: Evaluation of oxidant-reinforced extraction variables on overall bleaching optimization

TAPPI Journal ◽  
2013 ◽  
Vol 12 (10) ◽  
pp. 33-41 ◽  
Author(s):  
BRIAN N. BROGDON
Keyword(s):  
Response Surface ◽  
Chlorine Dioxide ◽  
North American ◽  
Yield Loss ◽  
Alkaline Extraction ◽  
Kraft Pulps ◽  
Pulp Bleaching ◽  
Response Surface Models ◽  
Elemental Chlorine ◽  
Surface Models

This investigation evaluates how higher reaction temperatures or oxidant reinforcement of caustic extraction affects chlorine dioxide consumption during elemental chlorine-free bleaching of North American hardwood pulps. Bleaching data from the published literature were used to develop statistical response surface models for chlorine dioxide delignification and brightening sequences for a variety of hardwood pulps. The effects of higher (EO) temperature and of peroxide reinforcement were estimated from observations reported in the literature. The addition of peroxide to an (EO) stage roughly displaces 0.6 to 1.2 kg chlorine dioxide per kilogram peroxide used in elemental chlorine-free (ECF) bleach sequences. Increasing the (EO) temperature by Δ20°C (e.g., 70°C to 90°C) lowers the overall chlorine dioxide demand by 0.4 to 1.5 kg. Unlike what is observed for ECF softwood bleaching, the presented findings suggest that hot oxidant-reinforced extraction stages result in somewhat higher bleaching costs when compared to milder alkaline extraction stages for hardwoods. The substitution of an (EOP) in place of (EO) resulted in small changes to the overall bleaching cost. The models employed in this study did not take into account pulp bleaching shrinkage (yield loss), to simplify the calculations.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

Systematic Defect Identification through Layout Snippet Clustering

2010 ◽  
Author(s):  
Wing Chiu Tam ◽  
Osei Poku ◽  
R. D. (Shawn) Blanton
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Yield Loss ◽  
Defect Identification ◽  
Clustering Techniques ◽  
Dominant Component

Abstract Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

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