Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

Capacitance Characterization of Gate to LDD Overlap Region to Understand Subtle Fail Modes in Advanced Node Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Edmund Banghart ◽  
Kevin Davidson ◽  
Yu Zhang ◽  
Jagar Singh ◽  
...  
Keyword(s):  
Work Function ◽  
Case Studies ◽  
Failure Mode ◽  
Defect Mode ◽  
Device Under Test ◽  
Root Cause ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Lightly Doped Drain

Abstract This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.

Timing Problems Due to Spacer Bridging in a Sub-100 nm Product

2008 ◽  
Author(s):  
Jan van Hassel
Keyword(s):  
Atomic Force Microscope ◽  
Yield Loss ◽  
Silicide Formation ◽  
Process Stability ◽  
Time Resolved ◽  
Atomic Force ◽  
Defect Localization ◽  
Lightly Doped Drain ◽  
Modified Test ◽  
Comprehensive Study

Abstract In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.

Characterization of the SiO2/SiC Interface with Impedance Spectroscopy

2009 ◽  
Vol 615-617 ◽  
pp. 501-504 ◽  
Author(s):  
Pawel A. Sobas ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson
Keyword(s):  
Impedance Spectroscopy ◽  
Ionic Conduction ◽  
Semiconductor Interface ◽  
Transfer Processes ◽  
Capacitance Voltage ◽  
Dc Bias ◽  
The One ◽  
Cv Measurements ◽  
Mos Structures

Using impedance spectroscopy (IS) for the characterization of SiO2/4H-SiC (MOS) structures, insight on the capacitive and resistive contributions in different physical regions of the MOS structures is obtained. Changing the DC bias conditions, semiconductor, interface as well as oxide traps can be detected. The MOS capacitance, as extracted from IS data, is different from the one obtained using capacitance voltage (CV) measurements, due to the possibility of distinguishing different charge transfer processes using IS. For instance, in the investigated capacitors, a clear contribution is revealed from ionic conduction processes at bias voltages close to zero.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

2007 ◽  
Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel
Keyword(s):  
Failure Mode ◽  
Failure Modes ◽  
Fault Modeling ◽  
Mode Analysis ◽  
Root Cause ◽  
Failure Mode Analysis

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

2000 ◽  
Author(s):  
J. N. C. de Luna ◽  
M. O. del Fierro ◽  
J. L. Muñoz
Keyword(s):  
Flash Memory ◽  
Electromagnetic Interference ◽  
Yield Loss ◽  
High Amplitude ◽  
Physical Analysis ◽  
Input Buffer ◽  
Automated Test Equipment ◽  
Root Cause ◽  
Root Cause Identification ◽  
Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

Characterization of a Resistive Path to a Gate Node Using Tunneling Current Measurements

2010 ◽  
Author(s):  
Clifford Howard ◽  
Sam Subramanian ◽  
Kent Erington ◽  
Randall Mulder ◽  
Yuk Tsang ◽  
...  
Keyword(s):  
High Resistance ◽  
Tunneling Current ◽  
Resistance Measurement ◽  
Gate Leakage ◽  
Advanced Technologies

Abstract Advanced technologies with higher gate leakage due to oxide tunneling current enable detection of high resistance faults to gate nodes using a straight forward resistance measurement.

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