A 0.18 µm high resolution bandpass delta-sigma modulator for acceleration transducer applications

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.

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A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) ◽

10.1109/dcis51330.2020.9268617 ◽

2020 ◽

Author(s):

Alejandro Suanes ◽

Michele Dei ◽

Lluis Teres ◽

Francisco Serra-Graells

Keyword(s):

High Resolution ◽

Low Power ◽

Delta Sigma Modulator ◽

Delta Sigma ◽

Calibration Free ◽

Ip Block

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Experimental Demonstration of Ideal Noise Shaping in Resonant Tunneling Delta-Sigma Modulator for High resolution, Wide Band A/D Converters

10.7567/ssdm.2005.i-2-3 ◽

2005 ◽

Author(s):

K. Maezawa ◽

M. Sakou ◽

W. Matsubara ◽

T. Mizutani ◽

H. Matsuzaki

Keyword(s):

High Resolution ◽

Resonant Tunneling ◽

Wide Band ◽

Noise Shaping ◽

Experimental Demonstration ◽

Delta Sigma Modulator ◽

Delta Sigma

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A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

Electronics ◽

10.3390/electronics8101093 ◽

2019 ◽

Vol 8 (10) ◽

pp. 1093 ◽

Cited By ~ 4

Author(s):

Lee ◽

Song ◽

Roh

Keyword(s):

High Resolution ◽

Fourth Order ◽

Power Efficiency ◽

Dynamic Range ◽

Oxide Semiconductor ◽

Total Power ◽

Signal To Noise ◽

Chopper Stabilization ◽

Delta Sigma Modulator ◽

Delta Sigma

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

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