A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0.5 μm 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 μm × 5 μm in 0.5 μm CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 μW), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.
Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications
