scholarly journals Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications

2013 ◽  
Vol 2013 ◽  
pp. 1-4
Author(s):  
Hung-Chi Chu ◽  
Jin-Fa Lin ◽  
Dong-Ting Hu
Keyword(s):  
Process Model ◽  
Performance Metrics ◽  
Pulse Generator ◽  
Single Mode ◽  
Low Complexity ◽  
Cmos Process ◽  
Flip Flop ◽  
Double Edge ◽  
Layout Area ◽  
Generator Design

A low complexity dual-mode pulse-triggered FF design for wireless baseband processing is presented in this paper. It supports both single-edge- and double-edge-triggered operations subject to a mode select control. Due to the novelty in pulse generator design, the layout area overhead is only 8% when compared with other single-mode counterpart design. Postlayout simulations in TSMC 1P6M 0.18 μm CMOS process model also indicate that the proposed design is as efficient as its single-mode counterpart in various performance metrics.

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

2019 ◽  
Vol 29 (08) ◽  
pp. 2050123 ◽  
Author(s):  
Neethu Anna Sabu ◽  
K. Batri
Keyword(s):  
Vlsi Design ◽  
Cmos Technology ◽  
Flip Flop ◽  
Circuit Performance ◽  
Power Efficient ◽  
Transmission Gate ◽  
Double Edge ◽  
Speed Performance ◽  
Layout Area ◽  
Power Delay Product

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).

scholarly journals Realization of DVCCTA Based Versatile Modulator

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Neeta Pandey ◽  
Rajeshwari Pandey ◽  
Aseem Sayal ◽  
Manan Tripathi
Keyword(s):  
Process Model ◽  
Pulse Generator ◽  
Model Parameters ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
Frequency Modulator ◽  
Amplitude Modulator ◽  
Differential Voltage Current Conveyor

A Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) based versatile modulator is proposed which can work as an amplitude modulator, frequency modulator, delta modulator, and sigma delta modulator. The modulator operational scheme uses pulse generator as a core and its output is used as carrier signal. A DVCCTA based pulse generator is proposed first and subsequently configured as different modulators. Compact realization is the key feature of the proposed circuit as it uses two DVCCTA; a grounded resistor and a grounded capacitor hence are appropriate for IC realization. The functionality of the proposed circuit is verified through SPICE simulations using TSMC 0.25 μm CMOS process model parameters. The performance parameters such as power dissipation and noise for various modulator schemes are also obtained.

scholarly journals Low Power and Low Complexity Flip-Flop Design using MIFGMOS

2018 ◽  
Vol 7 (3.1) ◽  
pp. 183
Author(s):  
U Ragavendran ◽  
M Ramachandran
Keyword(s):  
Low Power ◽  
Cochlear Implants ◽  
Low Complexity ◽  
Floating Gate ◽  
Cmos Process ◽  
Process Technology ◽  
Process Data ◽  
Flip Flop ◽  
Passive Devices ◽  
Sequential Logic

Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.  

A COMPACT CMOS POWER-ON-RESET PULSE GENERATOR DESIGN WITH LOW-POWER AND WIDE OPERATION RANGE

2010 ◽  
Vol 19 (06) ◽  
pp. 1365-1380 ◽  
Author(s):  
SUAT U. AY
Keyword(s):  
Low Power ◽  
Pulse Generator ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Detection Capability ◽  
Voltage Range ◽  
Low Voltage Operation ◽  
Reset Pulse ◽  
Generator Design

A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0.5 μm 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 μm × 5 μm in 0.5 μm CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 μW), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.

LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS

2009 ◽  
Vol 18 (01) ◽  
pp. 121-131
Author(s):  
YINGBO HU ◽  
RUNDE ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Pulse Generator ◽  
Cmos Technology ◽  
Flip Flop ◽  
Clock Network ◽  
Double Edge ◽  
Power Delay Product ◽  
Dissipation Power

In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 μm CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45–60%, 11–27% and 58–65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

A Bargraph IR-UWB pulse generator with Adaptive PSD for medical applications using a 130nm CMOS Process

2019 ◽  
Author(s):  
Luiz Carlos Moreira ◽  
Jose Fontebasso Neto ◽  
Walter Silva Oliveira ◽  
Elizabeth Fernandez ◽  
Ebert San Roman Castillo
Keyword(s):  
Pulse Generator ◽  
Medical Applications ◽  
Cmos Process
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