3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors
2014 ◽
Vol 40
(0)
◽
pp. 93-104
◽
Keyword(s):
Keyword(s):
2010 ◽
Vol 207
(8)
◽
pp. 1997-2001
◽