Design of a CMOS Low-Power Limiting Amplifier with RSSI Integrated Circuit for Low-Frequency Wake-Up Receivers

2018 ◽  
Author(s):  
Pattrakorn Chokchalermwat ◽  
Boonchuay Supmonchai
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Low Frequency ◽  
Limiting Amplifier

An Ultra-Low Power Subthreshold CMOS RSSI for Wake-Up Receiver

2016 ◽  
Vol 25 (08) ◽  
pp. 1650090 ◽  
Author(s):  
Yunzhen Wang ◽  
Shengxi Diao ◽  
Fujiang Lin ◽  
Haiquan Yuan
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Subthreshold Region ◽  
Ultra Low Power ◽  
Limiting Amplifier ◽  
Offset Voltage

This paper reports an ultra-low power received signal strength indicator (RSSI) for low frequency (LF) wake-up receiver. Topology theory analysis and subthreshold operation are performed to lower power consumption. Each gain stage of the subthreshold limiting amplifier (LA) employs cascade diode-connected loads to obtain high output impedance while maintaining low power. An offset cancelation circuit with different tail currents, which also operates in the subthreshold region, is employed to reduce the DC offset voltage. Unbalanced source-coupled pairs of subthreshold devices adopted in the full-wave rectification are optimized. A 45[Formula: see text]dB input dynamic range and [Formula: see text][Formula: see text]dB indicating error are achieved at 125[Formula: see text]KHz frequency. The prototype occupies an active area of 0.39[Formula: see text][Formula: see text][Formula: see text]0.28[Formula: see text]mm using CSMC 0.153-[Formula: see text]m complementary metal-oxide-semiconductor (CMOS) technology. With a 1.8[Formula: see text]V supply voltage, the overall current consumption is only 6[Formula: see text][Formula: see text]A.

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

Design Optimization of Low Power and Low Frequency Vibration Based MEMS Energy Harvester

2013 ◽  
Vol 475-476 ◽  
pp. 1624-1628
Author(s):  
Hasnizah Aris ◽  
David Fitrio ◽  
Jack Singh
Keyword(s):  
Low Power ◽  
Energy Harvester ◽  
Piezoelectric Materials ◽  
Geometry Optimization ◽  
Low Frequency ◽  
Substrate Thickness ◽  
Power Harvesting ◽  
Low Frequency Vibration ◽  
Length Width ◽  
Development And Utilization

The development and utilization of different structural materials, optimization of the cantilever geometry and power harvesting circuit are the most commonly methods used to increase the power density of MEMS energy harvester. This paper discusses the cantilever geometry optimization process of low power and low frequency of bimorph MEMS energy harvester. Three piezoelectric materials, ZnO, AlN and PZT are deposited on top and bottom of the cantilever Si substrate. This study focuses on the optimization of the cantilevers length, width, substrate thickness and PZe thickness in order to achieve lower than 600 Hz of resonant frequency. The harvested power for this work is in the range of 0.02 ~ 194.49 nW.

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