Low-thermal-resistance flip-chip fine package for 1-W voltage regulator IC

2002 ◽  
Author(s):  
F. Takamura ◽  
K. Tanaka ◽  
K. Mitsuka ◽  
H. Matsushita
Keyword(s):  
Thermal Resistance ◽  
Flip Chip ◽  
Voltage Regulator

Two-Layer Solder Resist Film with Low Young’s Modulus for High Reliability

2020 ◽  
Vol 2020 (1) ◽  
pp. 000307-000312
Author(s):  
YingHsuan Chou ◽  
Daichi Okamoto ◽  
Hidekazu Miyabe
Keyword(s):  
Thermal Resistance ◽  
Crack Resistance ◽  
Young’S Modulus ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Layer Structure ◽  
High Reliability ◽  
Bga Packages ◽  
Link Density

Abstract In this paper, we reveal the development of a novel two-layer Solder Resist (SR) film with low young’s modulus which consists of low young’s modulus layer that possesses excellent adhesion to substrate and thermal resistance layer which is composed of resins with high thermal resistance and great toughness. This novel two-layer SR film exhibits superior resolution and crack resistance. Furthermore, the amount of warpage is extremely low. In general, the material with low young’s modulus and high elongation is caused from weak cross-link density, resulting in poor thermal resistance and delamination which occurs when mounting at high temperature. Herein, we can inhibit delamination successfully by this new two-layer structure film with superior thermal resistance. The Coefficient of Thermal Expansion (CTE) of conventional SR for FC-BGA is 35 ppm, and modulus is 4.5 GPa, whereas, this advanced two-layer SR film exhibits CTE of 66 ppm, and modulus of 2.3 GPa. In order to compare the crack resistance between conventional SR and newly developed two-layer SR film, the film was laminated on BGA substrate (substrate size is 50 mm × 50 mm), patterned by photolithography and cured, and then, 25 mm × 25 mm chip was mounted on a BGA substrate by flip-chip bonder. Conducting thermal cycle test (TCT) and observing the number of cracks after 1000 cycles of TCT. The crack occurrence frequency of the conventional SR is 65 %, whereas that of the new two-layer SR film is 4 %. We proved clearly that high CTE and low young’s modulus demonstrate overwhelmingly high crack resistance. Besides, high resolution of this newly developed two-layer film enabled the formation of SR opening (SRO) as small as 40 μm. From the above results, the newly developed two-layer SR film with low young’s modulus is beneficial for the next generation high-density package, especially for the outermost layer of FC-BGA packages and interposers that require higher reliability.

scholarly journals Techniques to reduce thermal resistance in flip-chip GaN-based VCSELs

2017 ◽  
Vol 214 (8) ◽  
pp. 1600819 ◽  
Author(s):  
Saadat Mishkat-Ul-Masabih ◽  
John Leonard ◽  
Daniel Cohen ◽  
Shuji Nakamura ◽  
Daniel Feezell
Keyword(s):  
Thermal Resistance ◽  
Flip Chip

Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array Packages

2004 ◽  
Vol 126 (4) ◽  
pp. 449-456 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Forced Convection ◽  
Thermal Performance ◽  
Flip Chip ◽  
Transfer Problem ◽  
Printed Wiring Board ◽  
Heat Spreader ◽  
Plastic Ball ◽  
Ball Grid Array Packages

Enhancements to thermal performance of FC-PBGA packages due to underfill thermal conductivity, controlled collapse chip connection (C4) pitch, package to printed wiring board (PWB) interconnection through thermal balls, a heat spreader on the backside of the die, and an overmolded die with and without a heat spreader have been studied by solving a conjugate heat transfer problem. These enhancements have been investigated under natural and forced convection conditions for freestream velocities up to 2 m/s. The following ranges of parameters have been covered in this study: substrate size: 25–35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), underfill thermal conductivity: 0.6–3.0 W/(m K), C4 pitch: 250 μm and below, no thermal balls to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of a bare and an overmolded die. Based on our previous work, predictions in this study are expected to be within ±10% of measured data. The conclusions of the study are: (i) Thermal conductivity of the underfill in the range 0.6 to 10 W/(m K) has negligible effect on thermal performance of FC-PBGA packages investigated here. (ii) Thermal resistances decrease 12–15% as C4 pitch decreases below 250 μm. This enhancement is smaller with increase in die area. (iii) Thermal balls connected to the PTHs in the PWB decrease thermal resistance of the package by 10–15% with 9×9 array of thermal balls and PTHs compared to no thermal balls. The effect of die size on this enhancement is more noticeable on junction to board thermal resistance, Ψjb, than the other two package thermal metrics. (iv) Heat spreader on the back of the die decreases junction-to-ambient thermal resistance, Θja, by 6% in natural convection and by 25% in forced convection. (v) An overmolded die with a heat spreader provides better a thermal enhancement than a heat spreader on a bare die for freestream velocities up to about 1 m/s. Beyond 1 m/s, a heat spreader on bare die has better thermal performance.

The Design and Development of a 15 kV SiC Half-Bridge Multi-Chip Power Module for Medium Voltage Applications

2014 ◽  
Vol 2014 (1) ◽  
pp. 000751-000756 ◽  
Author(s):  
Z. Cole ◽  
J. Stabach ◽  
G. Falling ◽  
P. Killeen ◽  
T. McNutt ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
High Voltage ◽  
Flip Chip ◽  
Mechanical Design ◽  
Three Dimensional ◽  
Power Module ◽  
Design And Development ◽  
Modeling And Analysis ◽  
High Level ◽  
Three Dimensional Finite Element

In this work, the packaging design and development of a high voltage (> 15 kV), high current (120 A) silicon carbide (SiC) multi-chip power module (MCPM) will be presented. The module implements a MCPM packaging strategy which itself uses subassemblies to reduce manufacturing costs through reworkability. The use of solderless internal connections aids in reducing cost both by simplifying the assembly process as well as enabling a high level of flexibility in the manufacturing process in order to drive down costs by increasing yield. A wire bondless flip-chip die interconnection scheme has been developed in parallel with a more traditional wire bonded method. Both presented approaches utilize a common set of parts with minimal differences due to the divergent portions of each interconnection scheme. Device neutrality in this design ensures that a variety of die types from any manufacturer may be housed in a number of arrangements depending on the requirements of the end-use application without requiring significant redesign effort for each new application or improvement in device technology. The SiC MCPM is constructed using high temperature capable materials, enabling operation at high junction temperatures. This leads to the ability to design a small, low profile module with low parasitic inductances and a small junction to case thermal resistance. A low module thermal resistance makes it possible to significantly reduce the size and complexity of the cooling systems, ultimately, reducing the size of the system. Thus, this novel high voltage SiC MCPM represents a significant step forward in high voltage switching applications. This paper discusses the overall mechanical design of the SiC high voltage MCPM; the three-dimensional finite-element modeling and analysis of the thermal and electrical characteristics of the high voltage power module are also presented.

Thermal Performance of an Adhesive Bonded Superconducting Multichip Module (MCM) on a Gifford-McMahon Cryocooler

2011 ◽  
Vol 2011 (1) ◽  
pp. 000683-000689
Author(s):  
Ranjith John ◽  
Vladimir Dotsenko ◽  
Deepnarayan Gupta ◽  
Ajay Malshe
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Experimental Analysis ◽  
Power Dissipation ◽  
Flip Chip ◽  
Multichip Module ◽  
Future Trends ◽  
Test Bed ◽  
Single Chip ◽  
Free Environment

We report the experimental study of the thermal resistance of a flip chip bonded superconducting multichip module (MCM) in a liquid cryogen free environment. A 5×5 mm2 indium-tin bumped superconducting chip was flip chip bonded on a 1×1 cm2 superconducting carrier chip. A non-conductive adhesive was used as an underfill to enhance the robustness of the package. We designed a test bed where the LSCE module was mounted onto the cold head of a Gifford McMahon (GM) cryocooler. The module was conductively cooled down to 4 K and the thermal resistance between the chip and the carrier chip was analyzed. The experimental results showed that for the power dissipation (2 – 5 mW), which is typical for low temperature superconducting electronic LSCE devices, the thermal resistance was 20.1 +/− 1.9 K/W. Thermal model of the current LSCE package was investigated using COMSOL multi-physics. Theoretical estimates showed that for the current package setup the expected thermal resistance of the bump path to be 6.2 K/W. The discrepancy between the model and experimental analysis has been explained due to the presence of voids and inadequate bump contact area. To our knowledge, this is the first such experimental investigation of the thermal performance of adhesive bonded LSCE package on a cryocooler. This experimental analysis is of paramount importance for future trends in single chip and multichip module packaging of LSCE devices.

An Assessment of the Impact of Interconnect Strategies on Thermal Performance of GaAs Power Amplifier IC Devices

2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Wire Bond ◽  
Die Attach ◽  
The Impact

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.

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