Distribution of Step Heights of Electron and Hole Traps in SiON nMOS Transistors

2020 ◽  
Author(s):  
K. Tselios ◽  
B. Stampfer ◽  
J. Michl ◽  
E. Ioannidis ◽  
H. Enichlmair ◽  
...  
Keyword(s):  
Electron And Hole Traps ◽  
Nmos Transistors

Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors

2002 ◽  
Vol 49 (12) ◽  
pp. 2183-2192 ◽  
Author(s):  
Kwang-Hoon Oh ◽  
C. Duvvury ◽  
K. Banerjee ◽  
R.W. Dutton
Keyword(s):  
Deep Submicron ◽  
Nmos Transistors

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors

2005 ◽  
Vol 45 (5-6) ◽  
pp. 779-782 ◽  
Author(s):  
T. Schram ◽  
L.-Å Ragnarsson ◽  
G. Lujan ◽  
W. Deweerd ◽  
J. Chen ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Nmos Transistors

High-Performance Poly-Si Nanowire NMOS Transistors

2007 ◽  
Vol 6 (2) ◽  
pp. 206-212 ◽  
Author(s):  
Horng-Chih Lin ◽  
Chun-Jung Su
Keyword(s):  
High Performance ◽  
Si Nanowire ◽  
Nmos Transistors

scholarly journals CMOS Realization of All-Positive Pinched Hysteresis Loops

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
B. J. Maundy ◽  
A. S. Elwakil ◽  
C. Psychalinos
Keyword(s):  
Hysteresis Loop ◽  
Detailed Analysis ◽  
Hysteresis Loops ◽  
Nonlinear Circuits ◽  
Experimental Results ◽  
First Order ◽  
Pinched Hysteresis Loop ◽  
A Charge ◽  
Pinched Hysteresis ◽  
Nmos Transistors

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

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