Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors

2002 ◽  
Vol 49 (12) ◽  
pp. 2183-2192 ◽  
Author(s):  
Kwang-Hoon Oh ◽  
C. Duvvury ◽  
K. Banerjee ◽  
R.W. Dutton
Keyword(s):  
Deep Submicron ◽  
Nmos Transistors

Performance analysis of 22 nm deep submicron NMOS transistors

2015 ◽  
Author(s):  
Kim Ho Yeap ◽  
Jor Gie Liew ◽  
Siu Hong Loh ◽  
Humaira Nisar ◽  
Zairi Ismael Rizman
Keyword(s):  
Performance Analysis ◽  
Deep Submicron ◽  
Nmos Transistors

Flicker noise in deep submicron nMOS transistors

2000 ◽  
Vol 44 (7) ◽  
pp. 1239-1245 ◽  
Author(s):  
N. Lukyanchikova ◽  
N. Garbar ◽  
M. Petrichuk ◽  
E. Simoen ◽  
C. Claeys
Keyword(s):  
Flicker Noise ◽  
Deep Submicron ◽  
Nmos Transistors

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

2002 ◽  
Vol 49 (12) ◽  
pp. 2171-2182 ◽  
Author(s):  
Kwang-Hoon Oh ◽  
C. Duvvury ◽  
K. Banerjee ◽  
R.W. Dutton
Keyword(s):  
Current Distribution ◽  
Deep Submicron ◽  
Nmos Transistors

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

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