Excellent DIBL Immunity in Junctionless Transistor on a High-$k$ Buried Oxide

2017 ◽  
Author(s):  
M. Ehteshamuddin ◽  
Sajad A. Loan ◽  
M. Rafat
Keyword(s):  
Buried Oxide ◽  
Junctionless Transistor

Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review

2015 ◽  
Vol 1109 ◽  
pp. 257-261 ◽  
Author(s):  
Noraini Othman ◽  
Mohd Khairuddin Md Arshad ◽  
Syarifah Norfaezah Sabki ◽  
U. Hashim
Keyword(s):  
Oxide Thickness ◽  
Thin Body ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Device Structures ◽  
Junctionless Transistor ◽  
Channel Effects ◽  
Silicon Thickness

This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

scholarly journals Ground plane and selective buried oxide based planar junctionless transistor

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Asim M. Murshid ◽  
Faisal Bashir
Keyword(s):  
Electric Field ◽  
Ground Plane ◽  
Cutoff Frequency ◽  
Volume Depletion ◽  
Short Channel ◽  
Short Channel Effect ◽  
Buried Oxide ◽  
Channel Effect ◽  
Junctionless Transistor ◽  
20 Nm

Abstract In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves I ON/I OFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (f T) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

scholarly journals Nanodevices Tend to Be Round

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 330
Author(s):  
Georges Pananakakis ◽  
Gérard Ghibaudo ◽  
Sorin Cristoloveanu
Keyword(s):  
Diffusion Process ◽  
Thermal Diffusion ◽  
Cross Section ◽  
Gate Voltage ◽  
Supportive Evidence ◽  
Inversion Mode ◽  
Nanowire Transistor ◽  
Junctionless Transistor ◽  
Simulation Results ◽  
Thermal Diffusion Process

Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by smaller size, lower doping, and higher gate voltage. After defining the geometrical criterion for square-to-circle shift, simulation results are used to document the main consequences. This transition occurs naturally in nanowires thinner than 50 nm. The results are rather universal, and supportive evidence is gathered from inversion-mode Gate-All-Around (GAA) MOSFETs as well as from thermal diffusion process.

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