Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review

2015 ◽  
Vol 1109 ◽  
pp. 257-261 ◽  
Author(s):  
Noraini Othman ◽  
Mohd Khairuddin Md Arshad ◽  
Syarifah Norfaezah Sabki ◽  
U. Hashim
Keyword(s):  
Oxide Thickness ◽  
Thin Body ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Device Structures ◽  
Junctionless Transistor ◽  
Channel Effects ◽  
Silicon Thickness

This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

scholarly journals Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

2021 ◽  
Author(s):  
Mahsa Mehrad ◽  
Meysam Zareiee
Keyword(s):  
The Body ◽  
Maximum Temperature ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Novel Structure ◽  
Channel Effects ◽  
Channel Region

Abstract in this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly.The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

scholarly journals Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET

2017 ◽  
Vol 7 (4) ◽  
pp. 1899
Author(s):  
Mohammed Khaouani ◽  
Ahlam Guen-Bouazza
Keyword(s):  
Single Channel ◽  
Numerical Study ◽  
Drain Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel One ◽  
A Value ◽  
Device Structures ◽  
Channel Effects ◽  
The Impact

<p>Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number<em> </em>on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10<sup>4</sup>, while our four channels GAA MOSFET showed a value of 10<sup>3</sup>. In addition, a low value of drain induced barrier lowering<em> (DIBL) of </em>60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.</p>

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

2017 ◽  
Vol 9 (01) ◽  
pp. 67-72
Author(s):  
Sarvesh Dubey ◽  
Rahul Mishra
Keyword(s):  
Analytical Modeling ◽  
Threshold Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Simulation Data ◽  
Back Gate ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

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