Frequency Multiplier using Phase-Locked Loop

2020 ◽  
Author(s):  
Harish G Shettar ◽  
Sujata Kotabagi ◽  
Nagaratna Shanbhag ◽  
Sachin Naik ◽  
Rahul Bagali ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Frequency Multiplier

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process

2010 ◽  
Vol 56 (4) ◽  
pp. 411-416 ◽  
Author(s):  
Adam Zaziabl
Keyword(s):  
Low Power ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Center Frequency ◽  
Cmos Process ◽  
Clock Generation ◽  
Submicron Process ◽  
Submicron Cmos ◽  
Circuit Techniques

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

scholarly journals Novel 10 GHz Bio-Radar System Based on Frequency Multiplier and Phase-Locked Loop

2010 ◽  
Vol 21 (2) ◽  
pp. 208-217 ◽  
Author(s):  
Seong-Sik Myoung ◽  
Yong-Jun An ◽  
Jun-Ho Moon ◽  
Byung-Jun Jang ◽  
Jong-Gwan Yook
Keyword(s):  
Phase Locked Loop ◽  
Radar System ◽  
Frequency Multiplier

A NOVEL 10 GHZ SUPER-HETERODYNE BIO-RADAR SYSTEM BASED ON A FREQUENCY MULTIPLIER AND PHASE-LOCKED LOOP

2011 ◽  
Vol 19 ◽  
pp. 149-162 ◽  
Author(s):  
Seong-Sik Myoung ◽  
Yong-Jun An ◽  
Jong-Gwan Yook ◽  
Byung-Jun Jang ◽  
Jun-Ho Moon
Keyword(s):  
Phase Locked Loop ◽  
Radar System ◽  
Frequency Multiplier

scholarly journals Implementation of Phase Frequency Detector in Phase locked loop using Preset able modified TSPC D flip-flop

2019 ◽  
Vol 8 (12) ◽  
pp. 977-980
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Single Phase ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Technology Applications ◽  
Phase Clock ◽  
Frequency Detector

Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.

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