A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process

2010 ◽  
Vol 56 (4) ◽  
pp. 411-416 ◽  
Author(s):  
Adam Zaziabl
Keyword(s):  
Low Power ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Center Frequency ◽  
Cmos Process ◽  
Clock Generation ◽  
Submicron Process ◽  
Submicron Cmos ◽  
Circuit Techniques

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

scholarly journals 10-GHz wide tuning-range linear voltage-controlled oscillator

2021 ◽  
Author(s):  
Sameh Soliman
Keyword(s):  
High Speed ◽  
Tuning Range ◽  
Serial Communication ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Center Frequency ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Communication Circuits ◽  
Simulation Results

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.

scholarly journals 10-GHz wide tuning-range linear voltage-controlled oscillator

2021 ◽  
Author(s):  
Sameh Soliman
Keyword(s):  
High Speed ◽  
Tuning Range ◽  
Serial Communication ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Center Frequency ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Communication Circuits ◽  
Simulation Results

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

scholarly journals Semidigital PLL Design for Low-Cost Low-Power Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-9
Author(s):  
Ni Xu ◽  
Woogeun Rhee ◽  
Zhihua Wang
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detection ◽  
Linear Phase ◽  
Digital Converter ◽  
Clock Generation ◽  
Time To Digital Converter ◽  
Simulation Results

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

A Low Power and Low Current-Mismatch Charge Pump with Dynamic Current Compensation

2019 ◽  
Vol 28 (12) ◽  
pp. 1920007
Author(s):  
Lianxi Liu ◽  
Shaopu Gao ◽  
Junchao Mu ◽  
Zhangming Zhu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Charge Pump ◽  
Channel Length ◽  
Cmos Process ◽  
Modulation Effect ◽  
Current Compensation ◽  
High Output Impedance ◽  
Low Offset ◽  
High Output

A novel low power charge pump (CP) that minimizes the mismatch between the charging and the discharging currents is proposed in this paper. The switching circuit with dynamic current compensation is used to reduce the power consumption of the proposed CP. In addition, precise current replication which makes use of the resistors and the low offset operational amplifiers (OTA) can enable a reduction in current mismatch caused by process mismatch. Meanwhile, the high output impedance can reduce the current mismatch caused by the channel length modulation effect. Based on the 0.18[Formula: see text][Formula: see text]m deep-Nwell CMOS process, the proposed CP can reduce the overall power consumption by 56% compared with the CP without current compensation, reduce the current mismatch caused by process mismatch to less than 0.9% and reduce the current mismatch caused by the channel length modulation effect to less than 0.01% over the output voltage ranging from 0.3 to 1.5[Formula: see text]V with 1.8[Formula: see text]V supply.

scholarly journals A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Tzung-Je Lee ◽  
Chua-Chin Wang
Keyword(s):  
Power Consumption ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Supply Noise

A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.

A 224-448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process

2017 ◽  
Vol 59 (7) ◽  
pp. 1750-1755 ◽  
Author(s):  
Jeng-Han Tsai ◽  
Chia-Lung Lin ◽  
Yin-Ting Kuo
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
Cmos Process ◽  
Fully Integrated

A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

2005 ◽  
Vol 14 (05) ◽  
pp. 997-1006 ◽  
Author(s):  
ROBERT C. CHANG ◽  
LUNG-CHIH KUO ◽  
HOU-MING CHEN
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Low Power Cmos ◽  
Charge Pump Circuit ◽  
Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

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