Novel Standby Leakage Reduction Technique in SRAM Cell with Enhanced Read Data Stability by Dynamically Varying the Cell Ratio and Pull-up Ratio using Wordline

2020 ◽  
Author(s):  
Arjun Singh Yadav ◽  
Ankur Beohar ◽  
Sunanda Ambulker
Keyword(s):  
Reduction Technique ◽  
Cell Ratio ◽  
Leakage Reduction ◽  
Sram Cell

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

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