Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage

2012 ◽  
Author(s):  
V.O. Cherman ◽  
J. De Messemaeker ◽  
K. Croes ◽  
B. Dimcic ◽  
G. Van der Plas ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Thermal Storage ◽  
Through Silicon Vias ◽  
Front End ◽  
Silicon Vias

Synchrotron-based measurement of the impact of thermal cycling on the evolution of stresses in Cu through-silicon vias

2014 ◽  
Vol 115 (24) ◽  
pp. 243509 ◽  
Author(s):  
Chukwudi Okoro ◽  
Lyle E. Levine ◽  
Ruqing Xu ◽  
Klaus Hummler ◽  
Yaw Obeng
Keyword(s):  
Thermal Cycling ◽  
Through Silicon Vias ◽  
Silicon Vias ◽  
The Impact

Reliability Implications of Thermo-Mechanically and Electrically Induced Interfacial Sliding of Through-Silicon Vias in 3D Packages

2015 ◽  
Author(s):  
Lutz Meinshausen ◽  
Ming Liu ◽  
Tae-Kyu Lee ◽  
Indranath Dutta ◽  
Li Li
Keyword(s):  
Shear Stress ◽  
Thermal Cycling ◽  
Diffusional Creep ◽  
Fe Model ◽  
Element Analysis ◽  
Through Silicon Vias ◽  
Mechanical Responses ◽  
Interfacial Sliding ◽  
As Stress ◽  
Silicon Vias

In conjunction with micro bumps, Through-Silicon-Vias (TSVs) are used for die stacking, leading to reduced footprints and a higher performance due to shorter communication bus-length. However the large difference between the thermal expansion of silicon and copper and an increased temperature of the die stack due to Joule heating lead to shear stress at the interface between TSV and substrate. Temperature activated interfacial diffusion in combination with the shear stress leads to diffusional interfacial sliding, resulting in TSV pro- or intrusion. In addition, electromigration (EM) at the interface leads to TSV motion. Against this background the protrusion/intrusion of Cu TSVs (ø 10 μm, length 100 μm) during fast and slow rate thermal cycling (TC) and during EM experiments was investigated. Parallel to the experimental investigation a finite element analysis (FEA) was performed to study the micro-mechanical responses of Cu-filled TSV during thermal cycling. For this purpose interfacial sliding was incorporated into the FE model by diffusional creep mechanism. The FE model captures the main features being observed in experiments such as stress hysteresis and intrusion/protrusion of the TSV relative to Si substrate.

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

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