Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales
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9780791856895

Author(s):  
Pradeep Lall ◽  
Hao Zhang ◽  
Lynn Davis

The reliability consideration of LED products includes both luminous flux drop and color shift. Previous research either talks about luminous maintenance or color shift, because luminous flux degradation usually takes very long time to observe. In this paper, the impact of a VOC (volatile organic compound) contaminated luminous flux and color stability are examined. As a result, both luminous degradation and color shift had been recorded in a short time. Test samples are white, phosphor-converted, high-power LED packages. Absolute radiant flux is measured with integrating sphere system to calculate the luminous flux. Luminous flux degradation and color shift distance were plotted versus aging time to show the degradation pattern. A prognostic health management (PHM) method based on the state variables and state estimator have been proposed in this paper. In this PHM framework, unscented kalman filter (UKF) was deployed as the carrier of all states. During the estimation process, third order dynamic transfer function was used to implement the PHM framework. Both of the luminous flux and color shift distance have been used as the state variable with the same PHM framework to exam the robustness of the method. Predicted remaining useful life is calculated at every measurement point to compare with the tested remaining useful life. The result shows that state estimator can be used as the method for the PHM of LED degradation with respect to both luminous flux and color shift distance. The prediction of remaining useful life of LED package, made by the states estimator and data driven approach, falls in the acceptable error-bounds (20%) after a short training of the estimator.


Author(s):  
Hao Huang ◽  
Abhijit Dasgupta ◽  
Ehsan Mirbagheri ◽  
Srini Boddapati

The focus of this paper is on the stress-strain behavior and creep response of a pressure-sensitive adhesive (PSA) with and without carrier layers. This study consists of two phases. The first phase focuses on understanding of the effects of fabrication profiles, including bonding pressure, bonding temperature, bonding time, and aging time, on the PSA joint strength. This part of the study is used to identify an acceptable bonding and aging conditions for manufacturing a robust PSA bonded assembly. Specimens fabricated with this selected set of bonding process conditions are then used for mechanical characterization. The second phase focuses on the assembly’s mechanical behavior (stress-strain behavior and the creep curves) under different loading conditions, including loading stress, loading rate, and loading temperature. The mechanical behavior of PSA bonded assemblies is affected not only by the loading conditions, but also by the assembly architecture. The mechanical behaviors and failure modes of PSAs with and without carrier layers are compared. The reasons for these differences are also discussed.


Author(s):  
Yeasir Arafat ◽  
Rahul Panat ◽  
Indranath Dutta

Interconnects that can deform under monotonous and/or repeated loading are increasingly important to a new class of electronic devices used for wearable applications. Such interconnects integrate different material sets such as polymers and metallic conductors and are subjected to large strain levels. A typical method to overcome the material incompatibility involves the conductor in the form of a serpentine or an out-of-the plane buckled geometry. In this paper, we demonstrate a novel combination of interconnect materials that enables significant improvement in the interconnect stretchability using Indium over the state-of-the-art without affecting the system performance. This was achieved without the necessity of the serpentine interconnects geometry that significantly improves the routing density. The manufacturing method used for this approach is also described. Finally, we discuss the cost competitiveness of the materials and the manufacturing method to assess the commercial viability of this approach. (5nm)


Author(s):  
H. Y. Zhang ◽  
Xiao Yan ◽  
W. H. Zhu ◽  
Leon Lin

2.5-D package with through silicon vias (TSVs) on interposer has been envisioned as the most viable way in heterogeneous integration. In this work, several design approaches are considered in the thermal analysis and enhancements of a 2.5-D package with multi chips on through silicon interposer (TSI), which include overmolding materials, metal slug, lid attachment, pin fin heat sink and fan-driven heat sink cooling. The analysis models consist of two dummy flip chips on a silicon interposer to represent the logic die and memory die, respectively. Package submodels, especially the TSV ones, are analyzed with good modeling accuracy. Package thermal modeling indicates that the thermal conductivity of the epoxy overmolding has minimal effect on the thermal performance of copper slug package. Lid attachment further enhances the thermal performance through peripheral substrate attachment. Both designs largely rely on thermally conductive PCB (4L) to maximize power dissipation. Pin-fin heat sink, made of aluminum, can be mounted on the package top to further minimize thermal resistance and extend the power dissipation beyond 10W. For high power application, fan cooled heat sink is used to reduce excessive heat. Copper based aluminum heat sink can remove the heat of 120W from the bare-die package. Self heating due to high current density through the TSV is analyzed. The proposed analytical expression gives good prediction on the local TSV hot spot. It is demonstrated that a distributed TSV network design provides lower temperature rise, which shall have lower risk of failures and is preferred in practice.


Author(s):  
Frank Wei

During the fabrications of 2.5D and 3D advanced packages, the needs for intermediate thinning and planarization processes persistently exit. This paper highlights the attributes of successful implementations, i.e., increased performances and yields for these processes, which have been identified by the market requirements for a variety of applications. Different packages with different materials systems and product goals lead to different requirements. This paper includes the thinning and polishing of TSV wafers in bonded wafer pairs for Si IC devicess or interposers, the thinning of overmolded, reconstituted wafers in eWLB applications, and the planarizations of metal bumps and RDL features in PoP, CSP, or fine line-and-space (L/S) substrate fabrications.


Author(s):  
Munshi Basit ◽  
Mohammad Motalab ◽  
Jeffrey C. Suhling ◽  
John L. Evans ◽  
Pradeep Lall

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior degradations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 C) and elevated temperature aging (50, 75, 100, 125, and 150 C) were unexpectedly large. The measured stress-strain data demonstrated large reductions in stiffness, yield stress, ultimate strength, and strain to failure (up to 50%) during the first 6 months after reflow solidification. In this study, we have used both accelerated life testing and finite element modeling to explore how prior isothermal aging affects the overall reliability of PBGA packages subjected to thermal cycling. In the experimental work, an extensive test matrix of thermal cycling reliability testing has been performed using a test vehicle incorporating several sizes (5, 10, 15, 19 mm) of BGA daisy chain components with 0.4 and 0.8 mm solder joint pitches (SAC305). PCB test boards with 3 different surface finishes (ImAg, ENIG and ENEPIG) were utilized. In this paper, we concentrate on the reporting the results for a PBGA component with 15 mm body size. Before thermal cycling began, the assembled test boards were divided up into test groups that were subjected to several sets of aging conditions (preconditioning) including 0, 6, and 12 months aging at T = 125 °C. After aging, the assemblies were subjected to thermal cycling (−40 to +125 °C) until failure occurred. The Weibull data failure plots have demonstrated that the thermal cycling reliabilities of pre-aged assemblies were significantly less than those of non-aged assemblies. A three-dimensional finite element model of the tested 15 mm PBGA packages was also developed. The cross-sectional details of the solder ball and the internal structure of the BGA were examined by scanning electron microscopy (SEM) to capture the real geometry of the package. Simulations of thermal cycling from −40 to 125 C were performed. To include the effects of aging in the calculations, we have used a revised set of Anand viscoplastic stress-strain relations for the SAC305 Pb-free solder material that includes material parameters that evolve with the thermal history of the solder material. The accumulated plastic work (energy density dissipation) was used is the failure variable; and the Darveaux approach to predict crack initiation and crack growth was applied with aging dependent parameters to estimate the fatigue lives of the studied packages. We have obtained good correlation between our new reliability modeling procedure that includes aging and the measured solder joint reliability data. As expected from our prior studies on degradation of SAC material properties with aging, the reliability reductions were more severe for higher aging temperature and longer aging times.


Author(s):  
Hiroyuki Tsuritani ◽  
Toshihiko Sayama ◽  
Yoshiyuki Okamoto ◽  
Takeshi Takayanagi ◽  
Masato Hoshino ◽  
...  

The reliability of solder joints on printed circuit boards (PCBs) is significantly affected by thermal fatigue processes due to downsizing and high density packaging in electronic components. Accordingly, there is a strong desire in related industries for development of a new nondestructive inspection technology to detect fatigue cracks appearing in these joints. The authors have applied the SP-μCT, a synchrotron radiation X-ray microtomography system, to the nondestructive observation of such cracks. However, for planar objects such as PCB substrates, reconstruction of CT images is difficult due to insufficient X-ray transmission along the parallel axis of the substrate. In order to solve this problem, a synchrotron radiation X-ray laminography system was developed to overcome the size limits of such specimens. In this work, this system was applied to the three-dimensional, nondestructive observation of thermal fatigue cracks in solder joints, for which X-ray CT inspection has been extremely difficult. The observed specimens included two typical joint structures formed using Sn-3.0Ag-0.5Cu solder: (1) a fine pitch ball grid array (FBGA) joint specimen in which an LSI package is connected to a substrate by solder bumps 360 μm in diameter, and (2) a die-attached specimen in which a 3 mm square ceramic chip is mounted on a substrate. The optical system developed for use in X-ray laminography was constructed to provide a rotation axis with a 30° tilt from the right angle to the X-ray beam, and to obtain X-ray projection images via the beam monitor. The same solder joints were observed successively using the laminography system at beamline BL20XU at SPring-8, the largest synchrotron radiation facility in Japan. In the FBGA type specimen, fatigue cracks were clearly observed to appear at the periphery of the joint interface, and to propagate gradually to the inner regions of the solder bumps as thermal cycling proceeded. In contrast, in the die-attached joint specimen, micro-cracks were observed to appear and propagate through the thin solder layer. An important observation was that these micro-cracks become interconnected prior to propagation of the main fatigue crack. The fatigue crack propagation lifetime was also estimated in both specimens by measuring the crack surface area and calculating the average crack propagation rate through the three-dimensional images. Consequently, the sectional images obtained by the laminography system clearly show the process of crack propagation due to thermal cyclic loading.


Author(s):  
T. Calvin Tszeng

Despite being a critical phenomenon of tremendous technological significance in ultrasonic flip-chip and wire bonding processes of today’s microelectronic devices, interfacial bond formation still calls for better understanding at a fundamental level. The goal of the research is to improve these processes through better understanding and modeling of bond formation. This paper presents a micromechanics model that addresses increasing contact area during ultrasonic cyclic loading cycle. The micromechanics model provides interfacial shear stress as boundary condition to FEM simulations of ultrasonic bonding processes. Comparison between preliminary results and experimental data is conducted.


Author(s):  
Quang Nguyen ◽  
Jordan C. Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall

In this work, an investigation has been performed on hygrothermally induced die stresses in flip chip assemblies caused by moisture absorption by the underfill encapsulant. Silicon test chips were first applied to perform a variety of measurements of moisture and thermally induced die stresses in flip chip on laminate assemblies. The sample die stresses were first measured after underfill encapsulation and cure, and then subsequently after long term storage (10 years) at room temperature and ambient humidity. The assemblies were then exposed to and 85 °C and 85% RH high humidity harsh environment for various durations, and the die stresses were evaluated as a function of the exposure time. Finally, reversibility tests were conducted to see whether the effects of moisture uptake were permanent. After long term storage, the experimental measurements showed that the normal stresses in the flip chip die relaxed significantly, while the shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposure had strong effects, generating tensile die normal stress changes of up to 30 MPa in the flip chip assemblies. Thus, the initial compressive die normal stresses due to flip chip assembly were found to relax significantly during the moisture exposure. Upon fully redrying, it was observed that the moisture-induced stress changes were fully recovered. The results of the experimental measurements were subsequently correlated with predictions from finite element numerical simulations. When performing moisture diffusion modeling, the conventional method is to use a thermal analogy based on the similarity of governing equations of heat transfer and moisture diffusion. However, this method has some drawbacks including giving incorrect results when dealing with time- and temperature-dependent problems or discontinuities in the moisture concentrations at material boundaries. In this study, we have used a new feature in ANSYS v14 to perform coupled multi-physics simulations of the moisture diffusion process without the aforementioned limitations. The simulation results were found to show strong correlations with experimental measurements.


Author(s):  
Toshihiko Sayama ◽  
Hiroyuki Tsuritani ◽  
Yoshiyuki Okamoto ◽  
Masayoshi Kinoshita ◽  
Takao Mori

Fatigue damage in solder joints is one of the most significant factors in the failure of electronic components. Accordingly, many research studies on the fatigue lifetime evaluation of solder joints have been undertaken to improve the reliability of the components. The authors have devised a lap-joint specimen with high stiffness fixtures in order to carry out shear fatigue testing on thin solder joints, which have thickness of a few hundred μm and are manufactured via a reflow process similar to that used in actual printed circuit boards (PCBs). In this work, using the developed lap-joint specimen, the fatigue properties, including crack initiation and propagation of Sn-3.0Ag-0.5Cu solder joints were evaluated under low cycle shear loading conditions with creep deformation. The lap-joint specimen was fabricated by the reflow soldering of two copper adherend, and was assembled with high stiffness loading fixtures. The dimensions of the solder joint are 4 mm (length) × 2 mm (width), with a thickness ranging from 100 to 400 μm. In the shear fatigue test, under the assumption of thermal loading conditions of actual PCBs, the inelastic strain amplitude and total strain rate were set to from 0.5 to 1.2 % and 1×10−4 s−1, respectively. In addition, the fatigue crack initiation lifetime is defined as the number of cycles N20% at which the load amplitude has decreased by 20 % from the initial value. As the first study result, the experimental relations between the fatigue crack initiation lifetime and the inelastic strain range were obtained. Next, in order to apply the experimental data to the evaluation of fatigue crack initiation in actual solder joints via finite element analyses, the lifetime data were related to the calculated inelastic strain at the interface corners of the solder joint of the specimen, where fatigue cracks initiate due to strain concentration. Finally, assuming that the reduction of the load amplitude corresponds linearly to the fatigue crack length, the experimental relations between the fatigue crack propagation rate and J-integral range were also obtained. The experimental data are regarded to be valid, given a comparison to other crack propagation curves for solder obtained by tensile cyclic loading of a flat specimen with a center crack. Consequently, the developed lap-joint specimen with high rigidity is effective for acquiring the material properties regarding fatigue crack initiation and propagation in actual thin solder joints.


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