Power dissipation in deep submicron CMOS digital circuits

2002 ◽  
Author(s):  
R.X. Gu ◽  
M.I. Elmasry
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Deep Submicron ◽  
Submicron Cmos

POWER ESTIMATION AND POWER OPTIMAL COMMUNICATION IN DEEP SUBMICRON BUSES: ANALYTICAL MODELS AND STATISTICAL MEASURES

2002 ◽  
Vol 11 (06) ◽  
pp. 637-658 ◽  
Author(s):  
PAUL P. SOTIRIADIS ◽  
ANANTHA CHANDRAKASAN
Keyword(s):  
Analytical Model ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Power Estimation ◽  
Deep Submicron ◽  
Analytical Models ◽  
Energy Estimation ◽  
Statistical Measures ◽  
Efficiency Measures ◽  
Distribution Of Power

Reduction of power dissipation in digital circuits is a subject of research in industry and academia. A major component of power dissipation in modern microprocessors is due to their large interconnect networks which are responsible for the distribution of power and clocks as well as for the intra-chip communication. Communication is realized by data and address buses. In this paper we (i) discuss an analytical model for energy estimation in deep submicron buses, (ii) present statistical energy measures based on the analytical model, (iii) derive the energy limits of communication through buses, (iv) and introduce energy efficiency measures of communication.

Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

1996 ◽  
Vol 43 (9) ◽  
pp. 1407-1415 ◽  
Author(s):  
R. Bellens ◽  
G. Van den Bosch ◽  
P. Habas ◽  
J.-P. Mieville ◽  
G. Badenes ◽  
...  
Keyword(s):  
Deep Submicron ◽  
Submicron Cmos
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