Linear low-frequency filter using on-chip giga-ohm resistance

Author(s):  
Shinyu Chen ◽  
Robert Rieger
2019 ◽  
Vol 29 (07) ◽  
pp. 2050109
Author(s):  
Yan Li ◽  
Yong Liang Li

A novel capacitance multiplier is proposed to implement an ultra-low-frequency filter for physiological signal processing in biomedical applications. With the proposed multiplier, a simple first-order low-pass filter achieves a [Formula: see text]3-dB frequency of 33.4[Formula: see text]μHz with a 1-pF capacitance and a 20[Formula: see text]k[Formula: see text] resistance. This corresponds to a multiplication factor of as large as [Formula: see text]. By changing the controlling terminal, the [Formula: see text]3-dB frequency can be tuned in a wide range of 33.4[Formula: see text]μHz–6.3[Formula: see text]kHz.


2015 ◽  
Vol 645-646 ◽  
pp. 875-880
Author(s):  
Qiang Li ◽  
Xiao Wei Liu ◽  
Liang Yin ◽  
Jia Jun Zhou

A fourth-order cascade low-pass transconductance capacitor filter is designed, and the coefficients of the filter are calculated. For the implementation of large-time constants the current shunt technique and the current cancellation technique are employed in the operational transconductance amplifiers. The whole filter is simulated in Hspice, the the cutoff frequency is 150.2Hz and the THD of the filter is 65dB, which meet the technical requirements of the inertial applications.


1977 ◽  
Vol 20 (8) ◽  
pp. 1224-1227
Author(s):  
A. S. Glinchenko ◽  
M. K. Chmykh ◽  
S. V. Chepurnykh

2014 ◽  
Vol 63 (2) ◽  
pp. 024301
Author(s):  
Cheng Cong ◽  
Wu Fu-Gen ◽  
Zhang Xin ◽  
Yao Yuan-Wei

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1353
Author(s):  
Junsoo Ko ◽  
Minjae Lee

An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency offset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 μ W. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are −60.09 dBc/Hz at 1 kHz with a figure of merit (FOM) of 151.35 dB/Hz, and −106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed oscillator occupies 0.056 mm2 in a standard 0.18 μ m CMOS process.


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