Optimizing Gain of 5 GHz RF amplifier keeping minimum deviation in center frequency and noise figure

2011 ◽  
Author(s):  
Jai Narayan Tripathi ◽  
Prakash R. Apte ◽  
Jayanta Mukherjee
Keyword(s):  
Noise Figure ◽  
Center Frequency ◽  
Minimum Deviation ◽  
Rf Amplifier ◽  
5 Ghz

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

Research and Analysis of Tunable Differential N-Path Band-Pass Filter

2020 ◽  
pp. 2150055
Author(s):  
Shuxiang Song ◽  
Guolun Liu ◽  
Mingcan Cen ◽  
Chaobo Cai
Keyword(s):  
Bandpass Filter ◽  
Noise Figure ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Transmission Function ◽  
Center Frequency ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Circuit Structure

Traditional filters usually have low Q and gain values and it is difficult to adjust their center frequencies. Moreover, it is very complicated to analyze their transmission charateristics through conventional methods. Therefore, in this paper, a tunable differential N-path bandpass filter that uses a new adjoint network method to analyze the transmission characteristics of the differential N-path structure is proposed. The filter circuit adopts a novel circuit structure consisting of two differential N-path structures, two transconductance amplifiers and an off-chip transformer. The differential structure eliminates even harmonics, the transconductance amplifier increases the circuit gain and the off-chip transformer acts as a balun, improving the filter’s Q value and achieving impedance matching. Unlike the traditional switching capacitance method used for analyzing the differential circuit structure, the method proposed in this paper does not involve complicated calculus operations. In fact, the method greatly simplifies these complex operations, and the transmission function of the circuit can be obtained through simple algebraic operations. The proposed filter was designed using TSMC 180[Formula: see text]nm CMOS process. Simulation results for a differential four-path bandpass filter formed under 1.2[Formula: see text]V supply voltage show that the gain of the filter is greater than 8.5 dB, the center frequency can be adjusted from 0.1[Formula: see text]GHz to 1[Formula: see text]GHz, the in-band insertion loss S11 is greater than 10 dB, the out-of-band IIP3 is greater than 10 dBm, the out-of-band rejection is 28 dB and the noise figure is less than 2.2 dB at [Formula: see text][Formula: see text]MHz.

A 5-GHz inductor-noise cancelling receiver with 1.8 dB noise figure in 65nm LP CMOS

2016 ◽  
Author(s):  
Chuan Qin ◽  
Lei Zhang ◽  
Zhijian Pan ◽  
Li Zhang ◽  
Yan Wang ◽  
...  
Keyword(s):  
Noise Figure ◽  
Noise Cancelling ◽  
5 Ghz

A switchable bandstop-to-bandpass reconfigurable filter for cognitive radio applications

2016 ◽  
Vol 9 (4) ◽  
pp. 765-772 ◽  
Author(s):  
Hamza Nachouane ◽  
Abdellah Najid ◽  
Abdelwahed Tribak ◽  
Fatima Riouch
Keyword(s):  
Cognitive Radio ◽  
Frequency Control ◽  
Center Frequency ◽  
Pin Diodes ◽  
Half Wave ◽  
Rejection Level ◽  
Frequency Tunability ◽  
Quarter Wave ◽  
Operating Bandwidth ◽  
5 Ghz

This paper presents a simple reconfigurable bandpass filter switching from 2.4 to 5 GHz based on PIN diodes. The proposed filter is intended to add frequency-tunability to antenna systems used in cognitive radio applications. It consists of a bent connecting stub with two open-circuited quarter-wave stubs grounded via PIN diodes. By controlling the didoes states, the electrical length of the stubs can be switched from quarter-wave to half-wave and vice versa, so as to tune the filter center frequency. The proposed design approach consists of ensuring communication at 2.4 GHz while blocking the 5 GHz band in the ON state, whereas in the OFF state, the filter is intended to reject the 2.4 GHz band and passing the 5 GHz band. A prototype of the proposed filter is fabricated and measured to validate the proposed concept. Both simulated and measured results show a two-state filter with a wide tuning range from 2.4 to 5 GHz and a good stopband rejection level better than 40 dB. Moreover, a flat group delay of about 0.55–0.7 ns is achieved within the operating bandwidth in both states. The proposed filter is able to achieve simultaneous bandwidth and frequency control, showing an important tool to meet modern system requirements.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals 5GHz MMIC LNA Design Using Particle Swarm Optimization

2013 ◽  
Vol 5 (6) ◽  
pp. 257-262
Author(s):  
Low Wen Shin ◽  
Arjuna Marzuki .
Keyword(s):  
Particle Swarm Optimization ◽  
Integrated Circuit ◽  
Noise Figure ◽  
Particle Swarm ◽  
Low Noise ◽  
Design System ◽  
Stability Factor ◽  
Power Gain ◽  
Swarm Optimization ◽  
5 Ghz

This research presents an optimization study of a 5 GHz Monolithic Microwave Integrated Circuit (MMIC) design using Particle Swarm Optimization (PSO). MMIC Low Noise Amplifier (LNA) is a type of integrated circuit device used to capture signal operating in the microwave frequency. This project consists of two stages: implementation of PSO using MATLAB and simulation of MMIC design using Advanced Design System (ADS). PSO model that mimics the biological swarm behavior is developed to optimize the MMIC design variables in order to achieve the required circuit performance and specifications such as power gain, noise figure, drain current and circuit stability factor. Simulation results show that the proposed MMIC design fulfills the circuit stability factor and achieves a power gain of 19.73dB, a noise figure of 1.15 dB and a current of 0.0467A.

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

2021 ◽  
Vol 16 (4) ◽  
pp. 559-564
Author(s):  
Chao Huang ◽  
Wan-Jun Yin
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Input Device ◽  
Output Stage ◽  
Noise Amplifier ◽  
5 Ghz

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

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