Static power optimization of deep submicron CMOS circuits for dual VT technology

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1145/288548.289076 ◽

1998 ◽

Author(s):

Qi Wang ◽

Sarma B. K. Vrudhula

Keyword(s):

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

Static Power ◽

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Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1109/iccad.1998.742957 ◽

2002 ◽

Author(s):

Qi Wang ◽

S.B.K. Vrudhula

Keyword(s):

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

Static Power ◽

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Analytical semi-empirical model for SER sensitivity estimation of deep-submicron CMOS circuits

11th IEEE International On-Line Testing Symposium ◽

10.1109/iolts.2005.15 ◽

2005 ◽

Author(s):

T. Heijmen

Keyword(s):

Empirical Model ◽

Deep Submicron ◽

Cmos Circuits ◽

Sensitivity Estimation ◽

Submicron Cmos ◽

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Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron

2014 International Symposium on Integrated Circuits (ISIC) ◽

10.1109/isicir.2014.7029446 ◽

2014 ◽

Author(s):

Amir Zjajo ◽

Nick van der Meijs ◽

Rene van Leuken

Keyword(s):

Statistical Power ◽

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

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Combined subthreshold and gate-oxide leakage power reduction in deep-submicron CMOS Circuits

International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. ◽

10.1109/iceec.2004.1374524 ◽

2005 ◽

Author(s):

R.S. Guindi

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Cmos Circuits ◽

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A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.2006.4271839 ◽

2006 ◽

Author(s):

Baozhen Yu ◽

Michael L. Bushnell

Keyword(s):

Deep Submicron ◽

Cmos Circuits ◽

Dynamic Power ◽

Leakage Reduction ◽

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CAD tools for analysis of process variability effects in deep submicron CMOS circuits

2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering ◽

10.1109/sibircon.2008.4602572 ◽

2008 ◽

Author(s):

W. Kuzmicz ◽

E. Piwowarska ◽

A. Pfitzner ◽

D. Kasprowicz

Keyword(s):

Deep Submicron ◽

Cmos Circuits ◽

Cad Tools ◽

Process Variability ◽

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Relevance of Gate Current for the Functionality of Deep Submicron CMOS Circuits

31st European Solid-State Device Research Conference ◽

10.1109/essderc.2001.195303 ◽

2001 ◽

Author(s):

S. Schwantes ◽

W. Krautschneider

Keyword(s):

Deep Submicron ◽

Cmos Circuits ◽

Gate Current ◽

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A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1145/1165573.1165627 ◽

2006 ◽

Author(s):

Baozhen Yu ◽

Michael L. Bushnell

Keyword(s):

Deep Submicron ◽

Cmos Circuits ◽

Dynamic Power ◽

Leakage Reduction ◽

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Modeling the Impact of Input-to-Output Coupling Capacitance on Power Dissipation Estimation in Deep Submicron CMOS Circuits

2007 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2007.4348251 ◽

2007 ◽

Author(s):

Zhangcai Huang ◽

Na Li ◽

Sui Huang ◽

Y. Inoue

Keyword(s):

Power Dissipation ◽

Deep Submicron ◽

Output Coupling ◽

Cmos Circuits ◽

Coupling Capacitance ◽

Submicron Cmos ◽

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Analysis of Static Power Reduction Strategies in Deep Submicron CMOS Device Technology for Digital Circuits

10.1109/ispcc53510.2021.9609444 ◽

2021 ◽

Author(s):

G. Munirathnam ◽

Y. Murali Mohan Babu

Keyword(s):

Digital Circuits ◽

Deep Submicron ◽

Power Reduction ◽

Reduction Strategies ◽

Static Power ◽

Submicron Cmos ◽

Device Technology

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