A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

2015 ◽  
Vol 23 (11) ◽  
pp. 2671-2675 ◽  
Author(s):  
Myonglae Chu ◽  
Byoungho Kim ◽  
Byung-Geun Lee
Keyword(s):  
Cmos Technology ◽  
Pipeline Adc ◽  
Zero Crossing

A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC

2016 ◽  
Vol 25 (12) ◽  
pp. 1650155
Author(s):  
Dong-Woo Jee ◽  
Yunjae Suh ◽  
Hong-June Park ◽  
Jae-Yoon Sim
Keyword(s):  
Stability Problem ◽  
Cmos Technology ◽  
High Gain ◽  
Pipeline Adc ◽  
Level Crossing ◽  
Zero Crossing ◽  
Class Ab ◽  
Op Amp ◽  
Damping Control ◽  
Digitally Controlled

A digitally controlled operational amplifier (op-amp) with level-crossing-based approximation is proposed. A high gain is effectively obtained by means of a damping control without a stability problem occurring in the multiple gain stages. Compared to the previous version of the zero-crossing-based algorithmic approximation, the proposed scheme further improves the settling time with the class AB operation obtained by switching of multiple driving paths. For verification, the designed op-amp is applied to a 10-bit pipeline ADC and implemented in a 0.18[Formula: see text][Formula: see text]m CMOS technology. Measured results show that the designed op-amp successfully operates at 10-bit resolution, 10[Formula: see text]MSample/s pipeline ADC and achieves an effective gain of more than 60[Formula: see text]dB.

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology

2017 ◽  
Author(s):  
Siddharth Devarajan ◽  
Larry Singer ◽  
Dan Kelly ◽  
Steve Kosic ◽  
Tao Pan ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Pipeline Adc

scholarly journals Signal Conditioning ASIC for the Detection of Combustible Gases

2021 ◽  
Author(s):  
Shelja Kaushal ◽  
Ashwani K. Rana
Keyword(s):  
Power Consumption ◽  
Operating Temperature ◽  
Cmos Technology ◽  
Low Noise ◽  
Working Environment ◽  
Voltage Controlled Oscillator ◽  
Signal Conditioning ◽  
Control Room ◽  
Zero Crossing ◽  
Gas Concentration

In this paper, the signal conditioning ASIC has been designed for transferring the information regarding gas concentration from the hazardous environment of coal mines to the control room. The ASIC is designed to avoid danger in the hazardous working environment with features like high operating temperature, faster response, high sensitivity, and low power consumption. For the desired application, the different modules for ASIC including Low Noise Amplifier (LNA), Voltage Controlled Oscillator (VCO), and Zero Crossing Detector integrated with a buffer are designed based on 180nm CMOS technology node using SCL pdk files on Cadence Virtuoso tool. The overall power consumption of the designed ASIC is 3.92mW with a gain of ~15 and a frequency range of 10KHz to 200KHz for 0.1% gas concentration for a sensor with the operating temperature of ~150oC. The final output of the ASIC is 0V to 1.8V of the square wave which can be further transmitted to the control room.

scholarly journals DESIGN OF HIGH SPEED,6-BIT PIPELINE ADC WITH BUILT-IN DIGITAL ERROR CORRECTION UNIT USING SUBMICRON CMOS TECHNOLOGY.

2016 ◽  
Vol 4 (6) ◽  
pp. 519-524
Author(s):  
Manjuvani. K.M ◽  
◽  
Manasak chigateri ◽  
Manjunath KM ◽  
Sharanbasavaraj B. ◽  
...  
Keyword(s):  
Error Correction ◽  
High Speed ◽  
Cmos Technology ◽  
Pipeline Adc ◽  
Submicron Cmos

scholarly journals A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Yi Zhang ◽  
Qiao Meng ◽  
Changchun Zhang ◽  
Ying Zhang ◽  
Yufeng Guo ◽  
...  
Keyword(s):  
Single Channel ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Zero Crossing ◽  
Chip Area ◽  
Analog To Digital ◽  
Bootstrapped Switch ◽  
Foreground Calibration ◽  
Two Stages ◽  
Crossing Point

A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology

2008 ◽  
Author(s):  
Thomas Liechti ◽  
Armin Tajalli ◽  
Omer Can Akgun ◽  
Zeynep Toprak ◽  
Yusuf Leblebici
Keyword(s):  
Cmos Technology ◽  
Pipeline Adc
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