A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

2020 ◽  
Vol 10 (3) ◽  
pp. 27
Author(s):  
Andrea Ballo ◽  
Alfio Dario Grasso ◽  
Salvatore Pennisi ◽  
Chiara Venezia
Keyword(s):  
Resonant Frequency ◽  
Performance Optimization ◽  
Cmos Technology ◽  
Second Order ◽  
Silicon On Insulator ◽  
Circuit Performance ◽  
Fully Depleted ◽  
Current Consumption ◽  
28 Nm ◽  
Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

scholarly journals A Time-of-Flight Range Sensor Using Four-Tap Lock-In Pixels with High near Infrared Sensitivity for LiDAR Applications

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 116 ◽  
Author(s):  
Sanggwon Lee ◽  
Keita Yasutomi ◽  
Masato Morita ◽  
Hodaka Kawanishi ◽  
Shoji Kawahito
Keyword(s):  
High Speed ◽  
Near Infrared ◽  
Short Pulse ◽  
Time Of Flight ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
High Modulation

In this paper, a back-illuminated (BSI) time-of-flight (TOF) sensor using 0.2 µm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is developed for long-range laser imaging detection and ranging (LiDAR) application. A 200 µm-thick bulk silicon in the SOI substrate is fully depleted by applying high negative voltage at the backside for higher quantum efficiency (QE) in a near-infrared (NIR) region. The proposed SOI-based four-tap charge modulator achieves a high-speed charge modulation and high modulation contrast of 71% in a NIR region. In addition, in-pixel drain function is used for short-pulse TOF measurements. A distance measurement up to 27 m is carried out with +1.8~−3.0% linearity error and range resolution of 4.5 cm in outdoor conditions. The measured QE of 55% is attained at 940 nm which is suitable for outdoor use due to the reduced spectral components of solar radiation.

scholarly journals An Ultrafast Active Quenching Active Reset Circuit with 50% SPAD Afterpulsing Reduction in a 28 nm FD-SOI CMOS Technology Using Body Biasing Technique

Sensors ◽  
2021 ◽  
Vol 21 (12) ◽  
pp. 4014
Author(s):  
Mohammadreza Dolatpoor Lakeh ◽  
Jean-Baptiste Kammerer ◽  
Enagnon Aguénounon ◽  
Dylan Issartel ◽  
Jean-Baptiste Schell ◽  
...  
Keyword(s):  
Single Photon ◽  
Cmos Technology ◽  
The Body ◽  
Silicon On Insulator ◽  
Experimental Results ◽  
Fully Depleted ◽  
Body Biasing ◽  
Fast Quenching ◽  
28 Nm ◽  
Soi Cmos

An ultrafast Active Quenching—Active Reset (AQAR) circuit is presented for the afterpulsing reduction in a Single Photon Avalanche Diode (SPAD). The proposed circuit is designed in a 28 nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS technology. By exploiting the body biasing technique, the avalanche is detected very quickly and, consequently, is quenched very fast. The fast quenching decreases the avalanche charges, therefore resulting in the afterpulsing reduction. Both post-layout and experimental results are presented and are highly in accordance with each other. It is shown that the proposed AQAR circuit is able to detect the avalanche in less than 40 ps and reduce the avalanche charge and the afterpulsing up to 50%.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

2011 ◽  
Vol 3 (2) ◽  
pp. 99-105 ◽  
Author(s):  
Dixian Zhao ◽  
Ying He ◽  
Lianming Li ◽  
Dieter Joos ◽  
Wim Philibert ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Peak Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

scholarly journals State of the Art and Future Perspectives in Advanced CMOS Technology

Nanomaterials ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 1555 ◽  
Author(s):  
Henry H. Radamson ◽  
Huilong Zhu ◽  
Zhenhua Wu ◽  
Xiaobin He ◽  
Hongxiao Lin ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
3D Structure ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Strain Engineering ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Technology Roadmap ◽  
Innovative Methods ◽  
Device Processing

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

scholarly journals Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

2021 ◽  
Vol 11 (15) ◽  
pp. 6708
Author(s):  
Janne P. Aikio ◽  
Alok Sethi ◽  
Mikko Hietanen ◽  
Jere Rusanen ◽  
Timo Rahkonen ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Error Vector Magnitude ◽  
Fully Integrated ◽  
Power Added Efficiency ◽  
Wireless Applications ◽  
Ofdm Signal ◽  
New Radio

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

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