Low-power low-voltage analog electronic circuits using the flipped voltage follower

Author(s):  
Ramirez-Angulo ◽  
Carvajal ◽  
Torralba ◽  
Galan ◽  
Vega-Leal ◽  
...  
2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava

Two new high-performance output stages are proposed. These output stages are basically designed by using a flipped voltage follower (FVF). The proposed low-power and low-voltage output stages have utilized the advantages of the FGMOS technology. They are characterized by low-power dissipation, reduced power supply requirement, and larger bandwidth. By using FGMOS-based FVF in place of conventional FVF, the linearity of the output stages has been highly improved. The small-signal analysis of FGMOS-based FVF is done to show the bandwidth enhancement of conventional FVF. The circuits are simulated to demonstrate the effectiveness using SPICE, in TSMC 0.25-micron CMOS device models. The simulation results show that the power supply requirement of the proposed output stages is highly reduced and bandwidths are extremely higher than the conventional circuits.


Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angulo ◽  
A.J. Lopez-Martin ◽  
A. Torralba ◽  
J.A.G. Galan ◽  
...  

2017 ◽  
Vol 26 (07) ◽  
pp. 1750112 ◽  
Author(s):  
Surachoke Thanapitak ◽  
Prajuab Pawarangkoon ◽  
Chutham Sawigun

This paper presents a compact second-order bandpass filter developed by combining the well-known flipped voltage follower circuit as a transconductance network with two capacitors. Operated in the subthreshold region, the filter’s center frequency can be adjusted linearly by varying the bias current. Post-layout simulation using a 0.35-[Formula: see text]m CMOS process confirms the suitability of the proposed filter in low-voltage, low-power environment.


2012 ◽  
Vol 21 (03) ◽  
pp. 1250024 ◽  
Author(s):  
CHAIWAT SAKUL ◽  
KOBCHAI DEJHAN

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.


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