The flipped voltage follower: a useful cell for low-voltage low-power circuit design

2003 ◽  
Author(s):  
J. Ramirez-Angulo ◽  
R.G. Carvajal ◽  
A. Torralba ◽  
J. Galan ◽  
A.P. Vega-Leal ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Low Voltage ◽  
Power Circuit ◽  
Flipped Voltage Follower ◽  
Voltage Follower

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

2005 ◽  
Vol 52 (7) ◽  
pp. 1276-1291 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angulo ◽  
A.J. Lopez-Martin ◽  
A. Torralba ◽  
J.A.G. Galan ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Low Voltage ◽  
Power Circuit ◽  
Flipped Voltage Follower ◽  
Voltage Follower

scholarly journals High-Frequency and Low-Power Output Stages Based on FGMOS Flipped Voltage Follower

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Low Voltage ◽  
Bandwidth Enhancement ◽  
Small Signal Analysis ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Low Power Dissipation ◽  
Output Stages

Two new high-performance output stages are proposed. These output stages are basically designed by using a flipped voltage follower (FVF). The proposed low-power and low-voltage output stages have utilized the advantages of the FGMOS technology. They are characterized by low-power dissipation, reduced power supply requirement, and larger bandwidth. By using FGMOS-based FVF in place of conventional FVF, the linearity of the output stages has been highly improved. The small-signal analysis of FGMOS-based FVF is done to show the bandwidth enhancement of conventional FVF. The circuits are simulated to demonstrate the effectiveness using SPICE, in TSMC 0.25-micron CMOS device models. The simulation results show that the power supply requirement of the proposed output stages is highly reduced and bandwidths are extremely higher than the conventional circuits.

Double gate (DG)-SOI ratioed logic with symmetric DG load––a novel approach for sub 50 nm low-voltage/low-power circuit design

2004 ◽  
Vol 48 (10-11) ◽  
pp. 1727-1732 ◽  
Author(s):  
S. Mitra ◽  
A. Salman ◽  
D.P. Ioannou ◽  
C. Tretz ◽  
D.E. Ioannou
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Low Voltage ◽  
Double Gate ◽  
Power Circuit ◽  
Novel Approach

scholarly journals Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

2020 ◽  
Vol 10 (2) ◽  
pp. 20
Author(s):  
Amel Garbaya ◽  
Mouna Kotti ◽  
Mourad Fakhfakh ◽  
Esteban Tlelo-Cuautle
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Low Voltage ◽  
Surrogate Models ◽  
Modelling Technique ◽  
Current Conveyors ◽  
Jaya Algorithm ◽  
Power Circuit ◽  
Design And Optimization ◽  
Circuit Sizing

Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach offers interesting results.

A Flipped Voltage Follower Second-Order Bandpass Filter

2017 ◽  
Vol 26 (07) ◽  
pp. 1750112 ◽  
Author(s):  
Surachoke Thanapitak ◽  
Prajuab Pawarangkoon ◽  
Chutham Sawigun
Keyword(s):  
Low Power ◽  
Bandpass Filter ◽  
Low Voltage ◽  
Bias Current ◽  
Second Order ◽  
Center Frequency ◽  
Cmos Process ◽  
Subthreshold Region ◽  
Flipped Voltage Follower ◽  
Voltage Follower

This paper presents a compact second-order bandpass filter developed by combining the well-known flipped voltage follower circuit as a transconductance network with two capacitors. Operated in the subthreshold region, the filter’s center frequency can be adjusted linearly by varying the bias current. Post-layout simulation using a 0.35-[Formula: see text]m CMOS process confirms the suitability of the proposed filter in low-voltage, low-power environment.

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