Trading off reliability and power-consumption in ultra-low power systems

2003 ◽  
Author(s):  
A. Maheshwari ◽  
W. Burleson ◽  
R. Tessier
Keyword(s):  
Power Consumption ◽  
Power Systems ◽  
Low Power ◽  
Ultra Low Power

multiPULPly

2021 ◽  
Vol 17 (2) ◽  
pp. 1-27
Author(s):  
Adi Eliahu ◽  
Ronny Ronen ◽  
Pierre-Emmanuel Gaillardon ◽  
Shahar Kvatinsky
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Power Systems ◽  
Low Power ◽  
Network Inference ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Network Applications ◽  
Low Power Cmos ◽  
Neural Network Applications

Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by 1.5× to 4.5×.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals Ultra Low Power Consumption for Self-Oscillating Nanoelectromechanical Systems Constructed by Contacting Two Nanowires

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Nanoelectromechanical Systems ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

Ultra-Low-Power Electrophoretic Deposition of Silica Powder with Nonflammable Organic Solvent

2015 ◽  
Vol 654 ◽  
pp. 88-93
Author(s):  
Hideyuki Negishi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Electrophoretic Deposition ◽  
Particle Concentration ◽  
Deposition Time ◽  
Ultra Low Power ◽  
Silica Powder ◽  
Inorganic Particles ◽  
Uniform Coating ◽  
Electrical Insulation Properties

Although conventional organic solvents are used in electrophoretic deposition (EPD) owing to several advantages, they are hazardous because of their inflammability or ignition properties. In contrast, hydrofluoro ether (HFE) is nonflammable, polar and possesses excellent electrical insulation properties. In this study, methoxy-nonafluorobutane (MNFB), which is one of HFE was used as the solvent for the EPD of silica powder. Because the density of MNFB is larger than water, sedimentation of inorganic particles is slow. The deposition behavior in MNFB was similar to the EPD in conventional solvents, and was controlled by tuning the applied voltage, deposition time, and particle concentration. A uniform coating was obtained. Notably, the power consumed in this process was significantly lower than that in the EPD using conventional solvents. The current density was of the order of 10 nA/cm2; therefore, the electric power consumption for EPD using MNFB was less than 0.1% of those using conventional solvents. Therefore, MNFB can be used as an effective solvent for EPD because it is nonflammable, allows the application of high voltage, and enables the deposition of particles with low power consumption.

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

2012 ◽  
Vol 59 (12) ◽  
pp. 952-956 ◽  
Author(s):  
Dongsuk Jeon ◽  
Mingoo Seok ◽  
Zhengya Zhang ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Design Methodology ◽  
Ultra Low Power
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