A Dynamic Scan Chain Reordering for Low-Power VLSI Testing

2010 ◽  
Author(s):  
Chul-ki Baek ◽  
Insoo Kim ◽  
Jung-Tae Kim ◽  
Yong-Hyun Kim ◽  
Hyoung Bok Min ◽  
...  
Keyword(s):  
Low Power ◽  
Vlsi Testing ◽  
Dynamic Scan ◽  
Scan Chain

scholarly journals Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6111
Author(s):  
Sangjun Lee ◽  
Kyunghwan Cho ◽  
Jihye Kim ◽  
Jongho Park ◽  
Inhwan Lee ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Power Reduction ◽  
Wireless Sensor ◽  
Computational Time ◽  
Test Power ◽  
Significant Power ◽  
Highly Correlated ◽  
Scan Chain

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

Low Power Test Compression Technique for Designs with Multiple Scan Chain

2005 ◽  
Author(s):  
Youhua Shi ◽  
N. Togawa ◽  
M. Yanagisawa ◽  
T. Ohtsuki ◽  
S. Kimura
Keyword(s):  
Low Power ◽  
Compression Technique ◽  
Power Test ◽  
Test Compression ◽  
Low Power Test ◽  
Multiple Scan ◽  
Scan Chain

Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

2020 ◽  
Vol 20 (4) ◽  
pp. 390-404
Author(s):  
Dooyoung Kim ◽  
Jinuk Kim ◽  
Muhammad Ibtesam ◽  
Umair Saeed Solangi ◽  
Sungju Park
Keyword(s):  
Low Power ◽  
Test Method ◽  
Scan Test ◽  
Scan Chain

Low Power BIST with Smoother and Scan-Chain Reorder

2005 ◽  
Author(s):  
Nan-Cheng Lai ◽  
Sying-Jyan Wang ◽  
Yu-Hsuan Fu
Keyword(s):  
Low Power ◽  
Scan Chain

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing

2018 ◽  
Author(s):  
Yucong Zhang ◽  
Xiaoqin Wen ◽  
Stefan Holst ◽  
Kohei Miyase ◽  
Seiji Kajihara ◽  
...  
Keyword(s):  
Low Power ◽  
Clock Skew ◽  
Scan Testing ◽  
Scan Chain

Scan-chain masking technique for low power circuit testing

2009 ◽  
Author(s):  
Subhadip Kundu ◽  
Santanu Chattopadhyay
Keyword(s):  
Low Power ◽  
Circuit Testing ◽  
Power Circuit ◽  
Scan Chain
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