Integrated Automation Solution Driving Zero Yield Loss under Reticle Management

This investigation evaluates how higher reaction temperatures or oxidant reinforcement of caustic extraction affects chlorine dioxide consumption during elemental chlorine-free bleaching of North American hardwood pulps. Bleaching data from the published literature were used to develop statistical response surface models for chlorine dioxide delignification and brightening sequences for a variety of hardwood pulps. The effects of higher (EO) temperature and of peroxide reinforcement were estimated from observations reported in the literature. The addition of peroxide to an (EO) stage roughly displaces 0.6 to 1.2 kg chlorine dioxide per kilogram peroxide used in elemental chlorine-free (ECF) bleach sequences. Increasing the (EO) temperature by Δ20°C (e.g., 70°C to 90°C) lowers the overall chlorine dioxide demand by 0.4 to 1.5 kg. Unlike what is observed for ECF softwood bleaching, the presented findings suggest that hot oxidant-reinforced extraction stages result in somewhat higher bleaching costs when compared to milder alkaline extraction stages for hardwoods. The substitution of an (EOP) in place of (EO) resulted in small changes to the overall bleaching cost. The models employed in this study did not take into account pulp bleaching shrinkage (yield loss), to simplify the calculations.

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Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0273 ◽

2019 ◽

Author(s):

Satish Kodali ◽

Chen Zhe ◽

Chong Khiam Oh

Keyword(s):

Yield Loss ◽

Performance Metrics ◽

Root Cause ◽

Advanced Technologies ◽

Capacitance Voltage ◽

Defect Localization ◽

Cv Measurements ◽

Lightly Doped Drain ◽

Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

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Systematic Defect Identification through Layout Snippet Clustering

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0320 ◽

2010 ◽

Author(s):

Wing Chiu Tam ◽

Osei Poku ◽

R. D. (Shawn) Blanton

Keyword(s):

Design Process ◽

Integrated Circuit ◽

Yield Loss ◽

Defect Identification ◽

Clustering Techniques ◽

Dominant Component

Abstract Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

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Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0089 ◽

2000 ◽

Author(s):

J. N. C. de Luna ◽

M. O. del Fierro ◽

J. L. Muñoz

Keyword(s):

Flash Memory ◽

Electromagnetic Interference ◽

Yield Loss ◽

High Amplitude ◽

Physical Analysis ◽

Input Buffer ◽

Automated Test Equipment ◽

Root Cause ◽

Root Cause Identification ◽

Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

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BiCMOS Die Sort Yield Improvement from Isolation of a Localized Defect Mechanism and Precision TEM Cross Section

ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1997p0321 ◽

1997 ◽

Author(s):

J. Douglass ◽

T. D. Myers ◽

F. Tsai ◽

R. Ketcheson ◽

J. Errett

Keyword(s):

Electron Microscopy ◽

Cross Section ◽

Focused Ion Beam ◽

Yield Loss ◽

Process Analysis ◽

Ion Beam ◽

Yield Improvement ◽

Transmission Electron ◽

Defect Mechanism ◽

Water Residue

Abstract This paper describes how the authors used a combination of focused ion beam (FIB) microprobing, transmission electron microscopy (TEM), and data and process analysis to determine that localized water residue was causing a 6% yield loss at die sort.

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Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

10.31399/asm.cp.istfa2018p0300 ◽

2018 ◽

Author(s):

Seng Nguon Ting ◽

Hsien-Ching Lo ◽

Donald Nedeau ◽

Aaron Sinnott ◽

Felix Beaudoin

Keyword(s):

Failure Analysis ◽

High Performance ◽

Yield Loss ◽

Technology Development ◽

High Density ◽

High K ◽

Yield Learning ◽

Oxide Deposition ◽

Edge Profile ◽

High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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