scholarly journals Investigation Influence of Channel Transport on Output Characteristics in Sub-100nm Heterojunction Tunnel FET

Author(s):  
Yunhe Guan ◽  
Haifeng Chen ◽  
Siwei Huang ◽  
Feng Liang
2013 ◽  
Vol 60 (1) ◽  
pp. 92-96 ◽  
Author(s):  
Hsu-Yu Chang ◽  
Bruce Adams ◽  
Po-Yen Chien ◽  
Jiping Li ◽  
Jason C. S. Woo

2019 ◽  
Vol 11 (12) ◽  
pp. 1225-1230
Author(s):  
Suman Lata Tripathi

Low voltage application of Tunnel FET with steep subthreshold slope, has potential to replace its MOSFET counterpart for future scaling due to thermal limits imposed on nano-level transistors. Longer channel region increases the tunneling area results in increasing tunneling current and decreasing miller capacitance to improve device switching performance for digital application. A new pocket tunnel junction-less UTFET (JLUTFET) exploits increased channel length with U shape and high ON current capability of junction-less transistor provide better device performance in subthreshold region showing improvement in ION/IOFF(∼109) as compared to other similar conventional TFET and vertical TFET structures. The proposed nJLUTFET also shows lower drain induced barrier lowering (<20 mV/V) and near to ideal subthreshold slope (∼66 mV/decade). The temperature analysis plays a vital role to decide a stable ON and OFF-state performance of transistors. So, the proposed pocket JLUTFET is investigated for temperature variations (ranging 250–400 K) to characterize the performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed n-channel JLUTFET has been designed on visual TCAD 2D/3D device simulator.


2019 ◽  
Vol 40 (6) ◽  
pp. 1001-1004 ◽  
Author(s):  
Yunhe Guan ◽  
Zunchao Li ◽  
Hamilton Carrillo-Nunez ◽  
Yefei Zhang ◽  
Vihar P. Georgiev ◽  
...  

1993 ◽  
Vol 113 (6) ◽  
pp. 753-759 ◽  
Author(s):  
Kuniho Tanaka ◽  
Etsuo Sakoguchi ◽  
Eiji Yamada

2012 ◽  
Vol 132 (9) ◽  
pp. 922-930 ◽  
Author(s):  
Hirofumi Aoki ◽  
Tadashi Fukami ◽  
Kazuo Shima ◽  
Toshihiro Tsuda ◽  
Mitsuhiro Kawamura

Author(s):  
А.І. Панченко ◽  
◽  
А.А. Волошина ◽  
І.А. Панченко ◽  
А.І. Засядько ◽  
...  

Author(s):  
Yasunori Goto ◽  
Hiroomi Eguchi ◽  
Masaru Iida

Abstract In the automotive IC using thick-film silicon on insulator (SOI) semiconductor device, if the gettering capability of a SOI wafer is inadequate, electrical characteristics degradation by metal contamination arises and the yield falls. At this time, an automotive IC was made experimentally for evaluation of the gettering capability as one of the purposes. In this IC, one of the output characteristics varied from the standard, therefore failure analysis was performed, which found trace metal elements as one of the causes. By making full use of 3D perspective, it is possible to fabricate a site-specific sample into 0.1 micrometre in thickness without missing a failure point that has very minute quantities of contaminant in a semiconductor device. Using energy dispersive X-ray, it is possible to detect trace metal contamination at levels 1E12 atoms per sq cm. that are conventionally detected only by trace element analysis.


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