Low voltage application of Tunnel FET with steep subthreshold slope, has potential to replace its MOSFET counterpart for future scaling due to thermal limits imposed on nano-level transistors. Longer channel region increases the tunneling area results in increasing tunneling current
and decreasing miller capacitance to improve device switching performance for digital application. A new pocket tunnel junction-less UTFET (JLUTFET) exploits increased channel length with U shape and high ON current capability of junction-less transistor provide better device performance in
subthreshold region showing improvement in ION/IOFF(∼109) as compared to other similar conventional TFET and vertical TFET structures. The proposed nJLUTFET also shows lower drain induced barrier lowering (<20 mV/V) and near to ideal subthreshold
slope (∼66 mV/decade). The temperature analysis plays a vital role to decide a stable ON and OFF-state performance of transistors. So, the proposed pocket JLUTFET is investigated for temperature variations (ranging 250–400 K) to characterize the performance such as transfer characteristics,
Output characteristics and ION/IOFF ratio. The proposed n-channel JLUTFET has been designed on visual TCAD 2D/3D device simulator.