Pocket Vertical Junction-Less U-Shape Tunnel FET and Its Challenges in Nano-Scale Regime

2019 ◽  
Vol 11 (12) ◽  
pp. 1225-1230
Author(s):  
Suman Lata Tripathi
Keyword(s):  
Low Voltage ◽  
Tunneling Current ◽  
Channel Length ◽  
Vital Role ◽  
Subthreshold Slope ◽  
Subthreshold Region ◽  
Switching Performance ◽  
Tunnel Fet ◽  
Output Characteristics ◽  
Improve Device

Low voltage application of Tunnel FET with steep subthreshold slope, has potential to replace its MOSFET counterpart for future scaling due to thermal limits imposed on nano-level transistors. Longer channel region increases the tunneling area results in increasing tunneling current and decreasing miller capacitance to improve device switching performance for digital application. A new pocket tunnel junction-less UTFET (JLUTFET) exploits increased channel length with U shape and high ON current capability of junction-less transistor provide better device performance in subthreshold region showing improvement in ION/IOFF(∼109) as compared to other similar conventional TFET and vertical TFET structures. The proposed nJLUTFET also shows lower drain induced barrier lowering (<20 mV/V) and near to ideal subthreshold slope (∼66 mV/decade). The temperature analysis plays a vital role to decide a stable ON and OFF-state performance of transistors. So, the proposed pocket JLUTFET is investigated for temperature variations (ranging 250–400 K) to characterize the performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed n-channel JLUTFET has been designed on visual TCAD 2D/3D device simulator.

scholarly journals The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

2016 ◽  
Vol 6 (6) ◽  
pp. 2730
Author(s):  
Hak Kee Jung ◽  
Sima Dimitrijev
Keyword(s):  
Carrier Transport ◽  
Thermionic Emission ◽  
Tunneling Current ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Double Gate ◽  
Subthreshold Region ◽  
Channel Thickness ◽  
20 Nm ◽  
The Impact

<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

2016 ◽  
Vol 6 (6) ◽  
pp. 2730
Author(s):  
Hak Kee Jung ◽  
Sima Dimitrijev
Keyword(s):  
Carrier Transport ◽  
Thermionic Emission ◽  
Tunneling Current ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Double Gate ◽  
Subthreshold Region ◽  
Channel Thickness ◽  
20 Nm ◽  
The Impact

<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

scholarly journals Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance

2021 ◽  
Author(s):  
Jeetendra Singh ◽  
Debapriya Chakraborty ◽  
Naveen Kumar
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Channel Length ◽  
Subthreshold Slope ◽  
Effect Transistor ◽  
Output Characteristics ◽  
Output Conductance

Abstract In this paper, a dopingless nanotube field-effect transistor (DL-NT-FET) has been proposed and its performance analysis is done using a technology computer-aided design (TCAD) tool, ATLAS provided by Silvaco. The elimination of doping is brought in by the application of the charge-plasma (CP) technique. A comparative examination of transfer characteristics (I D -V GS ), transconductance (g m ), gate capacitances (C gs and C gd ), output characteristics (I D -V DS ), output conductance (g ds ), average subthreshold slope (AVSS), the threshold voltage (V t ), the ratio of on-current to off-current (I ON /I OFF ) and on-current has been made by varying the channel length (Lg), radius (R), gate work function (Φ), and temperature. Results revealed that increasing the channel length improves subthreshold slope with greater I ON /I OFF and less threshold voltage. It has been also noticed that increase in the radius of the nanotube or an increase in temperature results in just the opposite effect of that observed in the case of increasing channel length. The I OFF value increases significantly on increasing the temperature while the small degradation in the I ON has been noticed as a result of mobility degradation and velocity saturation. The I ON degrades 15% by increasing the temperature from 200K to 400K. The output conductance g ds also degrades on increasing the temperature. A proliferation of 39% is observed in the C gs at the V GS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the C gd for the same increment in the channel length.

Hot Carrier Effects in Self-aligned and Offset-Gated Polysilicon Thin-Film Transistors

2005 ◽  
Vol 888 ◽  
Author(s):  
N. Arpatzanis ◽  
A. T. Hatzopoulos ◽  
D. H. Tassis ◽  
Charalambos Dimitriadis ◽  
G. Kamarinos
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Transfer Characteristic ◽  
Channel Length ◽  
Subthreshold Slope ◽  
Hot Carriers ◽  
Subthreshold Region ◽  
Hot Carrier ◽  
Hot Carrier Effects ◽  
Post Stress

ABSTRACTThe effects of hot carriers on the transfer characteristics of self-aligned and offset-gated polysilicon thin-film transistors (TFTs), with channel length L = 10 μm and offset length ΔL = 2 μm, are investigated. In the self-aligned device, the on-state current is substantially reduced, whereas the subthreshold slope remains almost unaffected. In the offset gated device, the transfer characteristic is shifted first positively and then negatively, the on-state current is still substantially reduced and well-defined kinks are formed in the subthreshold region. The device degradation is found to become more pronounced in the offset gated device. A model explaining the post-stress performance of the offset-gated device is presented.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals Analysis of Simulated Output Characteristics of Gas Sensor Based on Graphene Nanoribbon

2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
A. Mahmoudi ◽  
M. Troudi ◽  
Y. Bergaoui ◽  
P. Bondavalli ◽  
N. Sghaier
Keyword(s):  
Gas Sensor ◽  
Gas Sensing ◽  
Channel Length ◽  
Graphene Nanoribbon ◽  
Sensor Model ◽  
Current Voltage ◽  
Output Characteristics ◽  
The Right ◽  
New Generation ◽  
The Given

This work presents simulated output characteristics of gas sensor transistors based on graphene nanoribbon (GNRFET). The device studied in this work is a new generation of gas sensing devices, which are easy to use, ultracompact, ultrasensitive, and highly selective. We will explain how the exposure to the gas changes the conductivity of graphene nanoribbon. The equations of the GNRFET gas sensor model include the Poisson equation in the weak nonlocality approximation with proposed sensing parameters. As we have developed this model as a platform for a gas detection sensor, we will analyze the current-voltage characteristics after exposure of the GNRFET nanosensor device to NH3gas. A sensitivity of nearly 2.7% was indicated in our sensor device after exposure of 1 ppm of NH3. The given results make GNRFET the right candidate for use in gas sensing/measuring appliances. Thus, we will investigate the effect of the channel length on the ON- and OFF-current.

Resistive Switching Behavior in Pt/La0.7Sr0.3MnO3/Nb0.05Bi0.95FeO3/Nb:SrTiO3 Ferroelectric Heterostructure

2014 ◽  
Vol 1061-1062 ◽  
pp. 333-336
Author(s):  
Yong Dan Zhu ◽  
Cheng Hu ◽  
An You Zuo
Keyword(s):  
Resistive Switching ◽  
Low Voltage ◽  
Switching Behavior ◽  
Good Time ◽  
Charge Redistribution ◽  
Resistive Switching Behavior ◽  
Switching Performance ◽  
Nonvolatile Memories ◽  
Interface Barrier ◽  
Non Destructive

we report reproducible resistive switching performance and relevant physical mechanism of Pt/La0.7Sr0.3MnO3/Nb0.05Bi0.95FeO3/Nb:SrTiO3 ferroelectric heterostructure which was fabricated by pulsed laser deposition. This device exhibits a nonvolatile resistive switching with a resistance ratio of up to 60 under 2V/-3V pulse voltages at room temperature. Low voltage readout, reliable resistance switching reproducibility and good time retention, indicating promise for non-destructive readout nonvolatile memories. In this metal/p-semiconductor/ferroelectric/n-semiconductor heterostructure, the mechanism of resistive switching behavior would be attributed to the ferroelectric polarization enhanced field-induced charge redistribution at the semiconductor/ferroelectric interface, resulting in the modulation of the interface barrier height. Keywords: Resistive switching, Ferroelectric resistive switching, Ferroelectric field effect.

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