A Review of Streamline Calibration Approaches for Digital Storage Oscilloscopes with Time-Interleaved Channels

The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.

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Timing Skew Calibration Method for TIADC-Based 20 GSPS Digital Storage Oscilloscope

Journal of Circuits System and Computers ◽

10.1142/s0218126616500079 ◽

2015 ◽

Vol 25 (02) ◽

pp. 1650007 ◽

Cited By ~ 9

Author(s):

Kuojun Yang ◽

Jiali Shi ◽

Shulin Tian ◽

Wuhuang Huang ◽

Peng Ye

Keyword(s):

Input Signal ◽

Sampling Rate ◽

Calibration Method ◽

Signal Frequency ◽

Accurate Estimation ◽

Storage Oscilloscope ◽

Digital Storage ◽

Digital Storage Oscilloscope ◽

Time Interleaved ◽

Timing Skew

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). When input signal frequency is very high, timing skews have significant effect on distortion. Therefore, a new timing skew calibration method is proposed in this paper. This method is based on the truth that timing skews are related to the product of the outputs of sub-ADCs. After timing skews are estimated, the digital controlled delay elements (DCDE) in ADC and phase locked loop (PLL) are utilized to calibrate timing skews. No auxiliary circuit and digital filter are needed for this calibration method. Simulation results show that the proposed method can estimate timing skew accurately. It is also proved that an accurate estimation can be obtained even the signal to noise ratio (SNR) of input signal is 20[Formula: see text]dB. The proposed method is employed to calibrate timing skews in a 16-channel TIADC-based 20[Formula: see text]GSPS digital storage oscilloscope (DSO). The experiment results demonstrate the usefulness of the proposed method. We can see that after timing skews are calibrated, the spectrum spurs have been effectively eliminated.

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