A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories

2011 ◽  
Author(s):  
Jonghong Kim ◽  
Junhee Cho ◽  
Wonyong Sung
Keyword(s):  
Error Correction ◽  
High Speed ◽  
Nand Flash ◽  
Flash Memories ◽  
Ldpc Decoder

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

Product Code Schemes for Error Correction in MLC NAND Flash Memories

2012 ◽  
Vol 20 (12) ◽  
pp. 2302-2314 ◽  
Author(s):  
Chengen Yang ◽  
Yunus Emre ◽  
Chaitali Chakrabarti
Keyword(s):  
Error Correction ◽  
Nand Flash ◽  
Flash Memories ◽  
Product Code
Sign in / Sign up

Export Citation Format

Share Document