Reliability of Physical Unclonable Function under Temperature and Supply Voltage Variations

Author(s):  
Manpreet Kaur ◽  
Rashid Rashidzadeh ◽  
Roberto Muscedere
2020 ◽  
Vol 1 (5) ◽  
Author(s):  
Yasuhiro Takahashi ◽  
Hiroki Koyasu ◽  
S. Dinesh Kumar ◽  
Himanshu Thapliyal

Abstract Silicon Physical Unclonable Function (PUF) is a general hardware security primitive for security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such radio frequency identification (RFID) and wireless sensor networks (WSN), etc. In this paper, we present a design of 4-bit QUALPUF which is based on static random access memory (SRAM) for low-power portable electronic devices and then shows the post-layout simulation and measurement results. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 $$\upmu$$ μ m standard CMOS process with 1.8 V supply voltage. The 4-bit QUALPUF occupies 58.7$$\times$$ × 15.7 $$\upmu \mathrm {m}^{2}$$ μ m 2 of layout area. The post-layout simulation results illustrate that the uniqueness calculated from the inter-die HDs of the 4-bit QUALPUF is 47.58%, the average reliability is 95.10%, and the the energy dissipation is 29.73 fJ/cycle/bit. The functional measurement results of the fabricated chip are the same as the post-layout simulation results.


Cryptography ◽  
2021 ◽  
Vol 5 (3) ◽  
pp. 23
Author(s):  
Riccardo Della Sala ◽  
Davide Bellizia ◽  
Giuseppe Scotti

In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on both Xilinx Spartan-6 and Artix-7 devices and the resulting design flows which allow to accurately balance the nominal delay of the different signal paths is outlined. The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation are able to fit in just 32 Configurable Logic Blocks (CLBs) without sacrificing steadiness, uniqueness and uniformity, thus outperforming most of the previously published FPGA-compatible PUFs.


2019 ◽  
pp. 82-87
Author(s):  
Nina P. Nestyorkina ◽  
Olga Yu. Kovalenko ◽  
Yulia A. Zhuravlyova

The article analyses the operational characteristics of 10W LED lamps with T8 bulb manufactured by ASD (Russia), Smartbuy (Taiwan), and VOLPE (PRC) and 18W FL with T8 bulb manufactured by PHILIPS (Poland) including the dependence of these lamps on the supply voltage. The results of measurements show that: a) the period of stabilisation of electric parameters and luminous flux of LED lamps does not cause discomfort of illumination unlike the said FL, the luminous flux of which at the moment of switching on is 70 % of the nominal value, which is reached after 13 minutes; b) with nominal voltage of supply network, the value of luminous flux of 10W ASD LED-T8R-STD LED lamp (Russia) is 6 % less than the declared one, and that of Smartbuy SBL-T8-10-64K-A (Taiwan) and VOLPE LED-T8-10W/DW/G13/FR/FIX/N (PRC) is even less; c) the general colour rendering index of all studied LED lamps is less than the declared one (72 instead of 80); d) the flicker index of all studied LED lamps does not exceed the declared value of 5 %; e) the characteristics of LED lamps almost do not depend on changes of the supply voltage within the range of ±10 %. The recommendations regarding the application of the studied LED lamps are given.


2020 ◽  
pp. 85-88 ◽  
Author(s):  
Nadezhda P. Kondratieva

The article describes the results of the study concerning the effect of the voltage level on current harmonic composition in greenhouses irradiators. It is found that its change affects the level of current harmonics of all types of the studied greenhouse irradiators. With decrease of nominal supply voltage by 10 %, the total harmonic distortion THDi decreases by 9 % for emitters equipped with high pressure sodium lamps (HPSL), by 10 % for emitters with electrode-less lamps and by 3 % for LED based emitters. With increase of nominal supply voltage by 10 %, THDi increases by 23 % for lighting devices equipped with HPSL, by 10 % for irradiators with electrode-less lamps and by 3 % for LED based emitters. Therefore, changes of supply voltage cause the least effect on the level of current harmonics of LED based emitters and then the emitters with electrode-less lamps. Change of the level of supply voltage causes the greatest effect on the level of current harmonics of HPSL based irradiators. Mathematical models of dependence of THDi on the level of supply voltage for greenhouse emitters equipped with LED, electrode-less lamps and HPSL lamps were formulated. These mathematical models may be used for calculations of total current when selecting transformers and supply cable lines for greenhouse lighting devices, for design of new or reconstruction of existing irradiation systems of greenhouse facilities, and for calculation of power losses in power supply networks of greenhouse facilities during feasibility studies for energy saving and energy efficiency increasing projects.


2020 ◽  
Vol 140 (12) ◽  
pp. 1297-1306
Author(s):  
Shu Takemoto ◽  
Kazuya Shibagaki ◽  
Yusuke Nozaki ◽  
Masaya Yoshikawa

2011 ◽  
Vol E94-C (6) ◽  
pp. 1072-1075
Author(s):  
Tadashi YASUFUKU ◽  
Yasumi NAKAMURA ◽  
Zhe PIAO ◽  
Makoto TAKAMIYA ◽  
Takayasu SAKURAI

2013 ◽  
Vol E96.C (4) ◽  
pp. 538-545
Author(s):  
Takeshi OKUMOTO ◽  
Kumpei YOSHIKAWA ◽  
Makoto NAGATA

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA

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