Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits

2013 ◽  
Vol E96.C (4) ◽  
pp. 538-545
Author(s):  
Takeshi OKUMOTO ◽  
Kumpei YOSHIKAWA ◽  
Makoto NAGATA
Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.


2010 ◽  
Vol 56 (4) ◽  
pp. 375-380 ◽  
Author(s):  
Paweł Gryboś ◽  
Piotr Kmon ◽  
Robert Szczygieł ◽  
Mirosław Żołądź

64 Channel ASIC for Neurobiology ExperimentsThis paper presents the design and measurements of 64 channel Application Specific Integrated Circuits (ASIC) for recording signals in neurobiology experiments. The ASIC is designed in 180 nm technology and operates with ± 0.9 V supply voltage. Single readout channel is built of AC coupling circuit at the input and two amplifier stages. In order to reduce the number of output lines, the 64 analogue signals from readout channels are multiplexed to a single output by an analogue multiplexer. The gain of the single channel can be set either to 350 V/V or 700 V/V. The low and the high cut-off frequencies can be tuned in 9 ÷ 90 Hz and in the 1.6 ÷ 24 kHz range respectively. The input referred noise is 7 μV rms in the bandwidth 90 Hz - 1.6 kHz and 9 μV rms in the bandwidth 9 Hz - 24 kHz. The single channel consumes 200 μW of power and this together with other parameters make the chip suitable for recording neurobiology signals.


2013 ◽  
Vol 10 (4) ◽  
pp. 155-162 ◽  
Author(s):  
L. Lanni ◽  
B. G. Malm ◽  
C.-M. Zetterling ◽  
M. Östling

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.


Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 325 ◽  
Author(s):  
Srinath Balasubramanian ◽  
Arunapriya Panchanathan ◽  
Bharatiraja Chokkalingam ◽  
Sanjeevikumar Padmanaban ◽  
Zbigniew Leonowicz

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.


Author(s):  
Franco Stellari ◽  
Alan J. Weger ◽  
Seongwon Kim ◽  
Dzmitry Maliuk ◽  
Peilin Song ◽  
...  

Abstract In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.


Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2042
Author(s):  
Vincenzo Stornelli ◽  
Leonardo Pantoli ◽  
Gianluca Barile ◽  
Alfiero Leoni ◽  
Emanuele D’Amico

This work presents the design of a discrete second-generation voltage conveyor (VCII) and its capability to be used as electronic interface for silicon photomultipliers. The design addressed here exploits directly at the transistor level, with commercial components, the proposed interface; the obtained performance is valuable considering both the discrete elements and the application. The architecture adopted here realizes a transimpedance amplifier that is also able to drive very high input impedance, as usually requested by photons detection. Schematic and circuital design of the discrete second-generation voltage conveyor is presented and discussed. The complete circuit interface requires a bias current of 20 mA with a dual 5V supply voltage; it has a useful bandwidth of about 106 MHz, and considering also the reduced dimensions, it is a good candidate to be used in portable applications without the need of high-cost dedicated integrated circuits.


2009 ◽  
Vol 08 (04n05) ◽  
pp. 389-402 ◽  
Author(s):  
ALEXANDER DESPOTULI ◽  
ALEXANDRA ANDREEVA

The decrease of energy consumption per 1 bit processing (ε) and power supply voltage (V dd ) of integrated circuits (ICs) are long-term tendencies in micro- and nanoelectronics. In this framework, deep-sub-voltage nanoelectronics (DSVN), i.e., ICs of ~1011–1012 cm-2 component densities operating near the theoretical limit of ε, is sure to find application in the next 10 years. In nanoelectronics, the demand on high-capacity capacitors of micron sizes sharply increases with a decrease of technological norms, ε and V dd . Creation of high-capacity capacitors of micron size to meet the challenge of DSVN and related technologies is considered. The necessity of developing all-solid-state impulse micron-sized supercapacitors on the basis of advanced superionic conductors (nanoionic supercapacitors) is discussed. Theoretical estimates and experimental data on prototype nanoionic supercapacitors with capacity density δC ≈ 100 μF/cm2 are presented. Future perspectives of nanoionic devices are briefly discussed.


2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.


1998 ◽  
Vol 08 (05n06) ◽  
pp. 589-604
Author(s):  
HORMOZ DJAHANSHAHI ◽  
MAJID AHMADI ◽  
GRAHAM A. JULLIEN ◽  
WILLIAM C. MILLER

This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular Arrays of a nonlinearly-loaded multiplier block form the core of multi-layer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Salient features of the present architecture, such as modularity and reduced interconnection problems and areas are highlighted and circuit design and improvements are presented for its universal building block. Other design issues such as supply voltage and power reduction and pin limitations are discussed together with experimental results.


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