A High Gain, Low Offset Time-Based Operational Amplifier for Capacitive Loads with 36MHz UGB and 70µA Quiescent Current

Author(s):  
Abirmoya Santra ◽  
Qadeer A. Khan
2015 ◽  
Vol 86 (7) ◽  
pp. 073102 ◽  
Author(s):  
J. E. Proctor ◽  
A. W. Smith ◽  
T. M. Jung ◽  
S. I. Woods

Author(s):  
Jeffin Joy ◽  
Swetha Clara Jose ◽  
Vijaya Kumar Kanchetla ◽  
Shubham Jain ◽  
Rajesh Zele
Keyword(s):  

2017 ◽  
Vol 2017 ◽  
pp. 1-10
Author(s):  
Jinpeng Qiu ◽  
Tong Liu ◽  
Xubin Chen ◽  
Yongheng Shang ◽  
Jiongjiong Mo ◽  
...  

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.


1980 ◽  
Vol 16 (6) ◽  
pp. 232 ◽  
Author(s):  
F. Krummenacher ◽  
J.-L. Zufferey

Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.


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