Study on the Influence of Gate Parasitic Inductance on the SiC MOSFET Switching Performance

Author(s):  
Shuai Liang ◽  
Zhibin Zhao ◽  
Peng Sun ◽  
Yumeng Cai
2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


2021 ◽  
Author(s):  
Hayden Carlton ◽  
John Harris ◽  
Alexis Krone ◽  
David Huitink ◽  
Md Maksudul Hossain ◽  
...  

Abstract The need for high power density electrical converters/inverters dominates the power electronics realm, and wide bandgap semiconducting materials, such as gallium nitride (GaN), provide the enhanced material properties necessary to drive at higher switching speeds than traditional silicon. However, lateral GaN devices introduce packaging difficulties, especially when attempting a double-sided cooled solution. Herein, we describe optimization efforts for a 650V/30A, GaN half-bridge power module with an integrated gate driver and double-sided cooling capability. Two direct bonded copper (DBC) substrates provided the primary means of heat removal from the module. In addition to the novel topology, the team performed electrical/thermal co-design to increase the multi-functionality of module. Since a central PCB comprised the main power loop, the size and geometry of the vias and copper traces was analyzed to determine optimal functionality in terms of parasitic inductance and thermal spreading. Thermally, thicker copper layers and additional vias introduced into the PCB also helped reduce hot spots within the module. Upon fabrication of the module, it underwent electrical characterization to determine switching performance, as well as thermal characterization to experimentally measure the total module’s thermal resistance. The team successfully operated the module at 400 V, 30 A with a power loop parasitic inductance of 0.89 nH; experimental thermal measurements also indicated the module thermal resistance to be 0.43 C/W. The overall utility of the design improved commensurately by introducing simple, yet effective electrical/thermal co-design strategies, which can be applied to future power modules.


2018 ◽  
Vol 64 ◽  
pp. 04005
Author(s):  
Jinyuan Li ◽  
Meiting Cui ◽  
Yujie Du ◽  
Junji Ke ◽  
Zhibin Zhao

Compared to the silicon power devices, silicon carbide device has shorter switch time. Hence, as a result of the faster transition of voltage (dv/dt) and current (di/dt) in SiC MOSFET, the influence of parasitic parameters on SiC MOSFET’s switching transient is more serious. This paper gives an experimental study of the influence of parasitic inductance on SiC MOSFET’s switching characteristics. Most significance parameters are the parasitic inductances of gate driver loop and power switching loop. These include the SiC MOSFET package’s parasitic inductance, interconnect inductance and the parasitic inductance of dc link PCB trace. This paper therefore focuses on analysis and comparison of different parasitic parameters under various operation conditions in terms of their effect on overvoltage, overcurrent and switching power loss.


2021 ◽  
Vol 18 (3) ◽  
pp. 113-122
Author(s):  
Si Huang ◽  
Zhong Chen

Abstract This article reports a double-sided stacked wire-bondless power module package for silicon carbide (SiC) power devices to achieve low parasitic inductance and improved thermal performance for high-frequency applications. The design, simulation, fabrication, and characterization of the power module are presented. A half-bridge module based on the SiC power MOSFETs is demonstrated with minimized parasitic inductance. Double-sided cooling paths are used to maximize heat dissipation. Besides conventional packaging materials used in the power module fabrication, a low-temperature cofired ceramic (LTCC) and nickel-plated copper balls are used in this module package. The LTCC acts as an interposer providing both electrical and thermal routings. The nickel-plated copper balls replace bond wires as the electrical interconnections for the SiC power devices. The electrical and thermo-mechanical simulations of the power module are performed, and its switching performance is evaluated experimentally.


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