Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Controller Design with Resistive Random-Access Memories (RRAM) for Field-Programmable Gate Arrays (FPGA)

2019 ◽  
Author(s):  
Hock Leong Chee ◽  
T. Nandha Kumar ◽  
Haider AF Almurib ◽  
Desmond Wen Hui Kang
Keyword(s):  
Controller Design ◽  
Random Access ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Look Up Table ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals Reduction in the number of LUT elements for control units with code sharing

2010 ◽  
Vol 20 (4) ◽  
pp. 751-761 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Jacek Bieganowski
Keyword(s):  
Field Programmable Gate Arrays ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Control Units ◽  
Linear Chains ◽  
Code Sharing ◽  
Field Programmable ◽  
Programmable Gate Arrays

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

scholarly journals Elevator controller based on implementing a random access memory in FPGA

2021 ◽  
Vol 11 (2) ◽  
pp. 1053
Author(s):  
Azzad Bader Saeed
Keyword(s):  
Software Package ◽  
Processing Time ◽  
Random Access ◽  
Random Access Memory ◽  
Clock Frequency ◽  
Access Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Field Programmable ◽  
Programmable Gate Arrays

Previous techniques of elevator controllers suffer from two main challenges: processing time, and software size. In this work these challenges have been overcame by implementing a controller random access memory (RAM) in a fast FPGA for a proto-type of two-floors elevator, as known the RAM and FPGA are fast devices. A look-up-table LUT (which is fast technique) has been proposed for this work, this LUT has represented a proposed relation between 10 and 7 lines, the states of the sensors and switches have been represented by the 10 input lines, and the commands for the motors of slide door and traction machine have been represented by the 7 output lines. The proposed LUT has been schematically realize by a (10×7) bits RAM which has been implemented in field programmable gate arrays (FPGA). The proposed system has been performed using 'ISE Design Suit' software package and FPGA Spartan6 SP-605 evaluation kit, the clock frequency of this FPGA is 200 MHz which is respectively high. The processing time and software size of the proposed controller had reached to 20ns and 3.75 MB, which they are less than that obtained from the results of previous techniques.

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