Reduction in the number of LUT elements for control units with code sharing

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

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Design of EMB-Based Moore FSMs

Journal of Circuits System and Computers ◽

10.1142/s0218126617501250 ◽

2017 ◽

Vol 26 (07) ◽

pp. 1750125 ◽

Cited By ~ 7

Author(s):

Małgorzata Kołopieńczyk ◽

Larysa Titarenko ◽

Alexander Barkalov

Keyword(s):

Control Unit ◽

Logic Circuits ◽

Embedded Memory ◽

Complexity Of Algorithms ◽

Gate Arrays ◽

Control Units ◽

Finite State ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

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Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs

Journal of Circuits System and Computers ◽

10.1142/s0218126619501317 ◽

2019 ◽

Vol 28 (08) ◽

pp. 1950131 ◽

Cited By ~ 1

Author(s):

Alexander Barkalov ◽

Larysa Titarenko ◽

Sławomir Chmielewski

Keyword(s):

Formal Method ◽

Field Programmable Gate Arrays ◽

Finite State Machines ◽

Logic Circuits ◽

State Machines ◽

Gate Arrays ◽

Finite State ◽

Field Programmable ◽

Programmable Gate Arrays

A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.

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