scholarly journals Elevator controller based on implementing a random access memory in FPGA

2021 ◽  
Vol 11 (2) ◽  
pp. 1053
Author(s):  
Azzad Bader Saeed
Keyword(s):  
Software Package ◽  
Processing Time ◽  
Random Access ◽  
Random Access Memory ◽  
Clock Frequency ◽  
Access Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Field Programmable ◽  
Programmable Gate Arrays

Previous techniques of elevator controllers suffer from two main challenges: processing time, and software size. In this work these challenges have been overcame by implementing a controller random access memory (RAM) in a fast FPGA for a proto-type of two-floors elevator, as known the RAM and FPGA are fast devices. A look-up-table LUT (which is fast technique) has been proposed for this work, this LUT has represented a proposed relation between 10 and 7 lines, the states of the sensors and switches have been represented by the 10 input lines, and the commands for the motors of slide door and traction machine have been represented by the 7 output lines. The proposed LUT has been schematically realize by a (10×7) bits RAM which has been implemented in field programmable gate arrays (FPGA). The proposed system has been performed using 'ISE Design Suit' software package and FPGA Spartan6 SP-605 evaluation kit, the clock frequency of this FPGA is 200 MHz which is respectively high. The processing time and software size of the proposed controller had reached to 20ns and 3.75 MB, which they are less than that obtained from the results of previous techniques.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

Study and Analysis a Powerful Debug Method for Smart Mobile Systems

2011 ◽  
Vol 130-134 ◽  
pp. 4270-4273
Author(s):  
Jian Guo Yuan ◽  
Sheng Gu
Keyword(s):  
Complex Systems ◽  
Mobile Phone ◽  
Software Package ◽  
Random Access ◽  
Random Access Memory ◽  
Exception Handling ◽  
Mobile Systems ◽  
Access Memory ◽  
Smart Mobile Phone ◽  
Smart Mobile

When dealing with such complex systems such as the software package of a smart mobile phone, it is necessary to apply powerful methods to detect and report errors when they occur. This paper probes and analyzes a powerful debug method called trap and exception handling, which is supported by the ARM platforms. The method can easily capture some valuable debug information. When a fatal error occurs during runtime or system detects an abnormal, a trap or an exception shall be logged and stored in the non-volatile random access memory (NVRAM). The information must be enough and easy for engineer to analyze the software error.

scholarly journals Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 584 ◽  
Author(s):  
Muhammad Irfan ◽  
Zahid Ullah ◽  
Ray C. C. Cheung
Keyword(s):  
Clock Cycle ◽  
Random Access ◽  
Packet Classification ◽  
Switching Activity ◽  
Content Addressable Memory ◽  
Gate Arrays ◽  
Lut Block ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Configurable Hardware

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

scholarly journals Reduction in the number of LUT elements for control units with code sharing

2010 ◽  
Vol 20 (4) ◽  
pp. 751-761 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Jacek Bieganowski
Keyword(s):  
Field Programmable Gate Arrays ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Control Units ◽  
Linear Chains ◽  
Code Sharing ◽  
Field Programmable ◽  
Programmable Gate Arrays

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

scholarly journals Memory Chips with Adjustable Configurations

VLSI Design ◽  
1999 ◽  
Vol 10 (2) ◽  
pp. 203-215
Author(s):  
Lizy Kurian John
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Programmable Logic ◽  
Cell Array ◽  
Gate Arrays ◽  
Mode Control ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Cell Arrays ◽  
Design Tradeoffs

In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.

Sign in / Sign up

Export Citation Format

Share Document